Typical Characteristics–AD548
Figure 19a. Unity Gain Follower
Figure 19b. Unity Gain Follower
Pulse Response (Large Signal)
Figure 19c. Unity Gain Follower
Pulse Response (Small Signal)
Figure 20a. Utility Gain Inverter
APPLICATION NOTES
Figure 20b. Utility Gain Inverter
Pulse Response (Large Signal)
Figure 20c. Unity Gain Inverter
Pulse Response (Small Signal)
The AD548 is a JFET-input op amp with a guaranteed maxi-
mum I
B
of less than 10 pA, and offset and drift laser-trimmed to
0.25 mV and 2
µV/°C
respectively (AD548C). AC specs in-
clude 1 MHz bandwidth, 1.8 V/µs typical slew rate and 8
µs
set-
tling time for a 20 V step to
±
0.01%—all at a supply current less
than 200
µA.
To capitalize on the device’s performance, a num-
ber of error sources should be considered.
The minimal power drain and low offset drift of the AD548
reduce self-heating or “warm-up” effects on input offset voltage,
making the AD548 ideal for on/off battery powered applica-
tions. The power dissipation due to the AD548’s 200
µA
supply
current has a negligible effect on input current, but heavy out-
put loading will raise the chip temperature. Since a JFET’s in-
put current doubles for every 10°C rise in chip temperature, this
can be a noticeable effect.
The amplifier is designed to be functional with power supply
voltages as low as
±
4.5 V. It will exhibit a higher input offset
voltage than at the rated supply voltage of
±
15 V, due to power
supply rejection effects. The common-mode range of the
AD548 extends from 3 V more positive than the negative supply
to 1 V more negative than the positive supply. Designed to
cleanly drive up to 10 kΩ and 100 pF loads, the AD548 will
drive a 2 kΩ load with reduced open loop gain.
OFFSET NULLING
Applying the AD548
Figure 21. Offset Null Configuration
LAYOUT
To take full advantage of the AD548’s 10 pA max input current,
parasitic leakages must be kept below an acceptable level. The
practical limit of the resistance of epoxy or phenolic circuit
board material is between 1
×
10
12
Ω
and 3
×
10
12
Ω.
This can
result in an additional leakage of 5 pA between an input of 0 V
and a –15 V supply line. Teflon or a similar low leakage material
(with a resistance exceeding 10
17
Ω)
should be used to isolate
high impedance input lines from adjacent lines carrying high
voltages. The insulator should be kept clean, since contaminants
will degrade the surface resistance.
A metal guard completely surrounding the high impedance
nodes and driven by a voltage near the common-mode input po-
tential can also be used to reduce some parasitic leakages. The
guarding pattern in Figure 22 will reduce parasitic leakage due
to finite board surface resistance; but it will not compensate for
a low volume resistivity board.
Unlike bipolar input amplifiers, zeroing the input offset voltage
of a BiFET op amp will not minimize offset drift. Using balance
Pins 1 and 5 to adjust the input offset voltage as shown in Fig-
ure 21 will induce an added drift of 0.24
µV/°C
per 100
µV
of
nulled offset. The low initial offset (0.25 mV) of the AD548C
results in only 0.6
µV/°C
of additional drift.
REV. C
–5–
AD [ ANALOG DEVICES ]
