AD526
TIMING AND CONTROL
Table I. Logic Input Truth Table
DIGITAL FEEDTHROUGH
Gain Code
A2 A1 A0 B
X
0
0
0
0
1
X
X
0
0
0
0
1
X
0
0
1
1
X
X
X
0
0
1
1
X
X
0
1
0
1
X
X
X
0
1
0
1
X
X
1
1
1
1
1
0
0
1
1
1
1
1
Control
CLK
(CS = 0)
1
0
0
0
0
0
0
1
1
1
1
1
1
Condition
Gain
Previous State
1
2
4
8
16
1
1
1
2
4
8
16
Condition
Latched
Transparent
Transparent
Transparent
Transparent
Transparent
Transparent
Latched
Latched
Latched
Latched
Latched
Latched
With either
CS
or
CLK
or both held high, the AD526 gain state
will remain constant regardless of the transitions at the A0, A1,
A2 or B inputs. However, high speed logic transitions will un-
avoidably feed through to the analog circuitry within the AD526
causing spikes to occur at the signal output.
This feedthrough effect can be completely eliminated by operat-
ing the AD526 in the transparent mode and latching the gain
code in an external bank of latches (Figure 36).
To operate the AD526 using serial inputs, the configuration
shown in Figure 36 can be used with the 74LS174 replaced by a
serial-in/parallel-out latch, such as the 54LS594.
A1
A0
A2
B
+5V
1 F
TIMING
SIGNAL
74LS174
+V
S
0.1 F
OUT
9 FORCE
NOTE: X = Don’t Care.
The specifications on page 3, in combination with Figure 35,
give the timing requirements for loading new gain codes.
16
A1
GAIN CODE
INPUTS
T
C
CLK
OR
CS
T
S
T
C
= MINIMUM CLOCK CYCLE
T
S
= DATA SETUP TIME
T
H
= DATA HOLD TIME
T
H
NOTE: THRESHOLD LEVEL FOR
GAIN CODE,
CS,
AND
CLK
IS 1.4V.
V
IN
–V
S
1
GAIN NETWORK
–
VALID DATA
15
14
13
12
11
B
10
A0
CS CLK
A2
LOGIC AND LATCHES
16
8
4
2
1
V
OUT
AD526
2
3
4
5
6
+
7
8 OUT
SENSE
0.1 F
Figure 35. AD526 Timing
Figure 36. Using an External Latch to Minimize Digital
Feedthrough
REV. D
–9–
AD [ ANALOG DEVICES ]
