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AD420AN-32 参数 Datasheet PDF下载

AD420AN-32图片预览
型号: AD420AN-32
PDF下载: 下载PDF文件 查看货源
内容描述: 串行输入16位4毫安20毫安, 0毫安- 20毫安DAC [Serial Input 16-Bit 4 mA-20 mA, 0 mA-20 mA DAC]
分类和应用:
文件页数/大小: 11 页 / 147 K
品牌: AD [ ANALOG DEVICES ]
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AD420
APPLICATIONS
CURRENT OUTPUT
Table IV. Buffer Amplifier Configuration
The AD420 can provide 4 mA–20 mA, 0 mA–20 mA, or 0 mA–
24 mA output without any active external components. Filter
capacitors C1 and C2 can be any type of low cost ceramic ca-
pacitors. To meet the specified full-scale settling time of 3 ms,
low dielectric absorption capacitors (NPO) are required. Suit-
able values are C1 = 0.01
µF
and C2 = 0.01
µF.
0.1 F
V
CC
V
LL
C1
2
RANGE
SELECT 1
RANGE
SELECT 2
CLEAR
LATCH
CLOCK
DATA IN
5
4
6
7
8
9
REF
OUT
14
15
REF
IN
11
GND
I
OUT
(4mA–20mA)
20
C2
21
23
0.1 F
R1
Open
Open
R
R
R2
Open
R
Open
2R
R3
0
R
R
2R
V
OUT
0 V–5 V
0 V–10 V
±
5 V
±
10 V
Suitable R = 5 kΩ.
OPTIONAL SPAN AND ZERO TRIM
For those users who would like lower than specified values of
offset and gain error, Figure 7 shows a simple way to trim these
parameters. Care should be taken to select low drift resistors
because they will affect the temperature drift performance of the
DAC.
The adjustment algorithm is iterative. The procedure for trim-
ming the AD420 in the 4 mA–20 mA mode can be accom-
plished as follows:
STEP I . . . OFFSET ADJUST
Load all zeros. Adjust RZERO for 4.00000 mA of output
current.
STEP II . . . GAIN ADJUST
Load all ones. Adjust RSPAN for 19.99976 mA (FS – 1 LSB) of
output current.
Return to STEP I and iterate until convergence is obtained.
V
CC
V
LL
0.1 F
RANGE
SELECT1
RANGE
SELECT2
CLEAR
LATCH
2
5
4
6
7
8
9
14
V
REF
500
RSPAN
10k
RZERO
GND
15
16
11
19
C1
20
C2
21
23
0.1 F
5k
RSPAN2
BOOST
I
OUT
(4mA–20mA)
18
R
LOAD
AD420
18
R
LOAD
Figure 5. Standard Configuration
DRIVING INDUCTIVE LOADS
When driving inductive or poorly defined loads connect a
0.01
µF
capacitor between I
OUT
(Pin 18) and GND (Pin 11).
This will ensure stability of the AD420 with loads beyond
50 mH. There is no maximum capacitance limit. The capacitive
component of the load may cause slower settling, though this
may be masked by the settling time of the AD420. A pro-
grammed change in the current may cause a back EMF voltage
on the output that may exceed the compliance of the AD420.
To prevent this voltage from exceeding the supply rails connect
protective diodes between I
OUT
and each of V
CC
and GND.
VOLTAGE-MODE OUTPUT
AD420
CLOCK
DATA IN
Since the AD420 is a single supply device, it is necessary to add
an external buffer amplifier to the V
OUT
pin to obtain a selec-
tion of bipolar output voltage ranges as shown in Figure 6.
V
CC
V
LL
0.1 F
2
RANGE
SELECT 1
RANGE
SELECT 2
CLEAR
LATCH
CLOCK
DATA IN
5
4
6
7
8
9
REF
OUT
14
15
REF
IN
11
GND
R1
V
OUT
17
V
OUT
20
C1
21
C2
23
0.1 F
Figure 7. Offset and Gain Adjust
AD420
Variation of RZERO between REF OUT (5 V) and GND leads
to an offset adjust range from –1.5 mA to 6 mA, (1.5 mA/V
centered at 1 V).
The 5 kΩ RSPAN2 resistor is connected in parallel with the
internal 40
sense resistor, which leads to a gain increase of
+0.8%.
As RSPAN is changed to 500
Ω,
the voltage on REF IN is
attenuated by the combination of RSPAN and the 30 kΩ
REF IN input resistance. When added together with RSPAN2
this results in an adjustment range of –0.8% to +0.8%.
R3
R2
Figure 6.
REV. F
–7–