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AD2S83AP 参数 Datasheet PDF下载

AD2S83AP图片预览
型号: AD2S83AP
PDF下载: 下载PDF文件 查看货源
内容描述: 可变分辨率分解器数字转换器 [Variable Resolution, Resolver-to-Digital Converter]
分类和应用: 转换器
文件页数/大小: 19 页 / 179 K
品牌: AD [ ANALOG DEVICES ]
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AD2S83
DIRECTION Output
CIRCUIT FUNCTIONS AND DYNAMIC PERFORMANCE
The DIRECTION (DIR) output indicates the direction of the
input rotation. Any change in the state of DIR precedes the
corresponding BUSY, DATA and RIPPLE CLOCK updates.
DIR can be considered as an asynchronous output and can
make multiple changes in state between two consecutive LSB
update cycles. This occurs when the direction of rotation of the
input changes but the magnitude of the rotation is less than 1 LSB.
COMPLEMENT
The
COMPLEMENT
input is an active low input and is inter-
nally pulled to +V
S
via 100 kΩ.
Strobing
DATA LOAD
and
COMPLEMENT
pins to logic LO
will set the logic HI bits of the AD2S83 counter to a LO state.
Those bits of the applied data which are logic LO will not
change the corresponding bits in the AD2S83 counter.
For Example:
Initial Counter State
Applied Data Word
Counter State after
DATA LOAD
Initial Counter State
Applied Data Word
Counter State after
DATA LOAD
and Complement
10101
11000
11000
10101
11000
00101
The AD2S83 allows the user great flexibility in choosing the
dynamic characteristics of the resolver-to-digital conversion to
ensure the optimum system performance. The characteristics
are set by the external components shown in Figure 1. The
Component Selection section explains how to select desired
maximum tracking rate and bandwidth values. The following
paragraphs explain in greater detail the circuit of the AD2S83
and the variations in the dynamic performance available to the
user.
Loop Compensation
The AD2S83 (connected as shown in Figure 1) operates as a
Type 2 tracking servo loop where the VCO/counter combination
and Integrator perform the two integration functions inherent in
a Type 2 loop.
Additional compensation in the form of a pole/zero pair is re-
quired to stabilize the loop.
This compensation is implemented by the integrator compo-
nents (R4, C4, R5, C5).
The overall response the converter is that of a unity gain second
order low-pass filter, with the angle of the resolver as the input
and the digital position data as the output.
The AD2S83 does not have to be connected as tracking con-
verter, parts of the circuit can be used independently. This is
particularly true of the Ratio Multiplier which can be used as a
control transformer. (For more information contact Motion
Control Applications.)
A block diagram of the AD2S83 is given in Figure 4.
In order to read the counter following a
DATA LOAD,
the
procedure below should be followed:
1. Place outputs in high impedance state (ENABLE = HI).
2. Present data to pins.
3. Pull
DATA LOAD
and
COMPLEMENT
pins to ground.
4. Wait 100 ns.
5. Remove data from pins.
6. Remove outputs from high impedance state (ENABLE =
LO).
7. Read outputs.
R5
AC ERROR
C4
SIN
COS
SIN
SIN
t
t
RATIO
MULTIPLIER
A, SIN ( – ) SIN
t
C5
PHASE
SENSITIVE
DEMODULATOR
R4
INTEGRATOR
DIGITAL
CLOCK
R6
DIRECTION
VCO
VELOCITY
Figure 4. Functional Diagram
REV. D
–11–