(ꢀVS = ꢀ12 V dc ꢀ 5%; VL = 5 V dc ꢀ 10%; TA = –40ꢁC to +85ꢁC)
AD2S83–SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Unit
SIGNAL INPUTS (SIN, COS)
Frequency1
0
1.8
20,000
2.2
150
Hz
V rms
nA
Voltage Level
Input Bias Current
Input Impedance
2.0
60
1.0
MΩ
REFERENCE INPUT (REF)
Frequency
Voltage Level
Input Bias Current
Input Impedance
0
1.0
20,000
8.0
150
Hz
V pk
nA
60
1.0
MΩ
PERFORMANCE
Repeatability
Allowable Phase Shift
Max Tracking Rate
1
+10
LSB
Degree
rps
rps
rps
(Signals to Reference)
10 Bits
12 Bits
–10
1040
260
65
14 Bits
16 Bits
User Selectable
16.25
rps
Bandwidth
ACCURACY
Angular Accuracy
Monotonicity
Missing Codes (16-Bit Resolution)
A, I
ꢀ
8 +1 LSB
arc min
Codes
Guaranteed Monotonic
A, I
4
VELOCITY SIGNAL
LINEARITY2, 3, 4
AD2S83AP
0 kHz–500 kHz
0.5 MHz–1 MHz
AD2S83IP
–40°C to +85°C
–40°C to +85°C
0.15
0.25
ꢀ
ꢀ
0.25
1.0
% FSR
% FSR
0 kHz–500 kHz
0.5 MHz–1 MHz
Reversion Error
AD2S83AP
–40°C to +85°C
–40°C to +85°C
0.25
0.25
ꢀ
ꢀ
0.5
1.0
% FSR
% FSR
–40°C to +85°C
–40°C to +85°C
0.5
1.0
3
ꢀ
ꢀ
1.0
1.5
% O/P
% O/P
mV
% FSR
V
AD2S83IP
DC Zero Offset5
Gain Scaling Accuracy
Output Voltage
Dynamic Ripple
1.5
ꢀ3
1 mA Load
Mean Value
8
1.0
% rms O/P
INPUT/OUTPUT PROTECTION
Analog Inputs
Analog Outputs
Overvoltage Protection
Short Circuit O/P Protection
8
8
V
mA
5.6
10.4
DIGITAL POSITION
Resolution
Output Format
Load
10, 12, 14, and 16
Bidirectional Natural Binary
Bits
3
LSTTL
INHIBIT6
Sense
Time to Stable Data
Logic LO to INHIBIT
240
35
390
490
110
ns
ns
ENABLE6
Logic LO Enables Position Output
Logic HI Outputs in High
Impedance State
ENABLE6/Disable Time
BYTE SELECT6
Sense
Logic HI
MS Byte DB1–DB8
LS Byte DB1–DB8
Logic LO
Time to Data Available
60
140
ns
SHORT CYCLE INPUTS
Internally Pulled High via
100 kΩ to +VS
SC1 SC2
0
0
1
1
0
1
0
1
10-Bit Resolution
12-Bit Resolution
14-Bit Resolution
16-Bit Resolution
–2–
REV. E
ADI [ ADI ]
