AD1881A
TIMING PARAMETERS
1
(GUARANTEED OVER OPERATING TEMPERATURE RANGE)
Parameter
RESET
Active Low Pulsewidth
RESET
Inactive to BIT_CLK Startup Delay
SYNC Active High Pulsewidth
SYNC Low Pulsewidth
SYNC Inactive to BIT_CLK Startup Delay
BIT_CLK Frequency
BIT_CLK Period
BIT_CLK Output Jitter
2
BIT_CLK High Pulsewidth
BIT_CLK Low Pulsewidth
SYNC Frequency
SYNC Period
Setup to Falling Edge of BIT_CLK
Hold from Falling Edge of BIT_CLK
BIT_CLK Rise Time
BIT_CLK Fall Time
SYNC Rise Time
SYNC Fall Time
SDATA_IN Rise Time
SDATA_IN Fall Time
SDATA_OUT Rise Time
SDATA_OUT Fall Time
End of Slot 2 to BIT_CLK, SDATA_IN Low
Setup to Trailing Edge of
RESET
(Applies to SYNC, SDATA_OUT)
Rising Edge of
RESET
to HI-Z Delay (ATE Test Mode)
Propagation Delay
RESET
Rise Time
NOTES
1
Guaranteed, not tested.
2
Output jitter is directly dependent on crystal input jitter.
Specifications subject to change without notice.
Symbol
t
RST_LOW
t
RST2CLK
t
SYNC_HIGH
t
SYNC_LOW
t
SYNC2CLK
t
CLK_PERIOD
t
CLK_HIGH
t
CLK_LOW
t
SYNC_PERIOD
t
SETUP
t
HOLD
t
RISECLK
t
FALLCLK
t
RISESYNC
t
FALLSYNC
t
RISEDIN
t
FALLDIN
t
RISEDOUT
t
FALLDOUT
t
S2_PDOWN
t
SETUP2RST
t
OFF
Min
50
Typ
833
Max
Unit
ns
µs
ns
µs
ns
MHz
ns
ps
ns
ns
kHz
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ns
80
19.5
162.8
12.288
81.4
36.62
36.62
40.69
40.69
48.0
20.8
2.5
4
4
4
4
4
4
4
4
750
44.76
44.76
5
5
2
2
2
2
2
2
2
2
0
15
10
10
10
10
10
10
10
10
10
25
15
50
REV. 0
–5–
AD [ ANALOG DEVICES ]
