AD1877
0
–10
–20
–30
–40
dBFS
–50
–60
–70
–80
–90
–100
–110
0.0
0.1
0.2
0.3
0.4
0.5
0.6
NORMALIZED F
S
0.7
0.8
0.9
1.0
TPC 7. Digital Filter Signal Transfer Function to F
S
LRCK
INPUT
BCLK
RDEDGE = LO
INPUT
BCLK
RDEDGE = HI
SOUT
OUTPUT
MSB-14
WCLK
OUTPUT
TAG
OUTPUT
LEFT TAG
MSB
LSB
RIGHT TAG
MSB
LSB
LEFT TAG
MSB
LSB
PREVIOUS DATA
LSB
ZEROS
LEFT DATA
MSB
MSB-1 MSB-2
LSB
ZEROS
RIGHT DATA
MSB
MSB-1 MSB-2
LSB
ZEROS
31
32
1
2
15
16
17
18
19
32
1
2
15
16
17
18
19
32
1
2
Figure 7. Serial Data Output Timing: Slave Mode, Right-Justified with No MSB Delay,
S/M = Hl, RLJUST = Hl, MSBDLY = Hl
LRCK
INPUT
BCLK
RDEDGE= LO
INPUT
BCLK
RDEDGE = HI
SOUT
OUTPUT
WCLK
INPUT
TAG
OUTPUT
LEFT TAG
MSB
LSB
RIGHT TAG
MSB
LSB
LEFT DATA
MSB
MSB-1 MSB-2
ZEROS
RIGHT DATA
MSB
MSB-1 MSB-2
1
2
3
4
17
1
2
3
4
17
ZEROS
LSB
LSB
ZEROS
Figure 8. Serial Data Output Timing: Slave Mode, Data Position Controlled by WCLK Input,
S/
M
= Hl, R
L
JUST= Hl,
MSBDLY
= LO
REV. A
–13–
AD [ ANALOG DEVICES ]
