AD1851/AD1861
TOTAL HARMONIC DISTORTION
R
F
Total harmonic distortion plus noise (THD+N) is defined as
the ratio of the square root of the sum of the squares of the val-
ues of the first 19 harmonics and noise to the value of the funda-
mental input frequency. It is usually expressed in percent (%).
THD+N is a measure of the magnitude and distribution of lin-
earity error, differential linearity error, quantization error and
noise. The distribution of these errors may be different, depend-
ing on the amplitude of the output signal. Therefore, to be most
useful, THD+N should be specified for both large (0 dB) and
small signal amplitudes (–20 dB and –60 dB).
The THD+N figure of an audio DAC represents the amount of
undesirable signal produced during reconstruction and playback
of an audio waveform. This specification, therefore, provides a
direct method to classify and choose an audio DAC for a
desired level of performance.
SETTLING TIME
REFERENCE
I
OUT
DAC
AUDIO
OUTPUT
INPUT LATCH
SERIAL-TO-PARALLEL
CONVERSION
CLOCK
LE
DATA
Figure 1. AD1851/AD1861 Functional Block Diagram
FUNCTIONAL DESCRIPTION
Settling time is the time required for the output of the DAC to
reach and remain within a specified error band about its final
value, measured from the digital input transition. It is a primary
measure of dynamic performance.
MIDSCALE ERROR
The AD1851/AD1861 is a complete monolithic PCM audio
DAC. No additional external components are required for op-
eration. As shown in Figure 1 above, each chip contains a volt-
age reference, an output amplifier, a DAC, an input latch and a
parallel input register.
The voltage reference consists of a bandgap circuit and buffer
amplifier. This combination of elements produces a reference
voltage that is unaffected by changes in temperature and age.
The DAC output voltage, which is derived from the reference
voltage, is also unaffected by these environmental changes.
The output amplifier uses both MOS and bipolar devices to
produce low offset, high slew rate and optimum settling time.
When combined with the on-chip feedback resistor, the output
op amp converts the output current of the AD1851/AD1861 to
a voltage output.
The DAC uses a combination of segmented decoder and R-2R
architecture to achieve consistent linearity and differential lin-
earity. The resistors which form the ladder structure are fabri-
cated with silicon chromium thin film. Laser-trimming of these
resistors further reduces linearity error, resulting in low output
distortion.
The input register and serial-to-parallel converter are fabricated
with CMOS logic gates. These gates allow the achievement of
fast switching speeds and low power consumption. This contrib-
utes to the overall low power dissipation of the AD1851/
AD1861.
Midscale error, or bipolar zero error, is the deviation of the ac-
tual analog output from the ideal output (0 V) when the 2s
complement input code representing half scale is loaded in the
input register.
D-RANGE DISTORTION
D-range distortion is equal to the value of the total harmonic
distortion + noise (THD+N) plus 60 dB when a signal level of
–60 dB below full scale is reproduced. D-range is tested with a
1 kHz input sine wave. This is measured with a standard A-
weight filter as specified by EIAJ Standard CP-307.
SIGNAL-TO-NOISE RATIO
The signal-to-noise ratio (SNR) is defined as the ratio of the
amplitude of the output when a full-scale output is present to
the amplitude of the output with no signal present. This is mea-
sured with a standard A-weight filter as specified by EIAJ
Standard CP-307.
REV. A
–5–
AD [ ANALOG DEVICES ]
