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5962-9684601QLX 参数 Datasheet PDF下载

5962-9684601QLX图片预览
型号: 5962-9684601QLX
PDF下载: 下载PDF文件 查看货源
内容描述: [IC 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP24, CERAMIC, DIP-24, Analog to Digital Converter]
分类和应用: 转换器模数转换器
文件页数/大小: 14 页 / 145 K
品牌: ADI [ ADI ]
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AD7892  
Pin  
No.  
Mnemonic  
Description  
16  
DB4/SCLK  
Data Bit 4/Serial Clock. When the device is in its parallel mode, this pin is Data Bit 4, a three-state  
TTL-compatible output. When the device is in its serial mode, this becomes the serial clock pin,  
SCLK. SCLK is an input and an external serial clock must be provided at this pin to obtain serial  
data from the AD7892. Serial data is clocked out from the output shift register on the rising edges  
of SCLK after RFS goes low.  
17  
DB3/RFS  
Data Bit 3/Receive Frame Synchronization. When the device is in its parallel mode, this pin is Data  
Bit 3, a three-state TTL-compatible output. When the device is in its serial mode, this becomes the  
receive frame synchronization input with RFS provided externally to obtain serial data from the  
AD7892.  
18  
19  
20  
DB2  
DB1  
DB0  
Data Bit 2. Three-state TTL-compatible output. This output should be left unconnected when the  
device is in its serial mode.  
Data Bit 1. Three-state TTL-compatible output. This output should be left unconnected when the  
device is in its serial mode.  
Data Bit 0 (LSB). Three-state TTL-compatible output. Output coding is two’s complement for  
AD7892-1 and AD7892-3 and straight (natural) binary for AD7892-2. This output should be left  
unconnected when the device is in its serial mode.  
21  
22  
23  
RD  
Read. Active low logic input which is used in conjunction with CS low to enable the data outputs.  
Chip Select. Active low logic input which is used in conjunction with RD to enable the data outputs.  
CS  
EOC  
End-of-Conversion. Active low logic output indicating converter status. The end of conversion is  
signified by a low going pulse on this line. The duration of this EOC pulse is nominally 100 ns.  
24  
CONVST  
Convert Start. Logic Input. A low-to-high transition on this input puts the track/hold into its hold  
mode and starts conversion.  
PIN CONFIGURATION  
DIP and SOIC  
V
1
2
3
4
5
6
7
8
9
24 CONVST  
23 EOC  
DD  
STANDBY  
V
V
22 CS  
IN2  
IN1  
21 RD  
REF OUT/REF IN  
AGND  
20 DB0 (LSB)  
19 DB1  
AD7892  
TOP VIEW  
(Not to Scale)  
MODE  
18 DB2  
DB11/LOW  
DB10/LOW  
17 DB3/RFS  
DB4/SCLK  
16  
15 DB5/SDATA  
14  
DB9 10  
DB8 11  
DB7 12  
DGND  
13 DB6  
–7–  
REV. C