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5962-9961003HXA 参数 Datasheet PDF下载

5962-9961003HXA图片预览
型号: 5962-9961003HXA
PDF下载: 下载PDF文件 查看货源
内容描述: [Dual Channel, 12-Bit, 105 MSPS IF Sampling A/D Converter With Analog Input Signal Conditioning]
分类和应用: 转换器
文件页数/大小: 20 页 / 1493 K
品牌: AD [ ANALOG DEVICES ]
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Dual Channel, 12-Bit 105 MSPS IF Sampling
A/D Converter with Analog Input
Signal Conditioning
includes two wide-dynamic range ADCs. Each ADC has a
transformer coupled front-end optimized for Direct-IF sampling.
The AD10200 has on-chip track-and-hold circuitry, and utilizes
an innovative architecture to achieve 12-bit, 105 MSPS perfor-
mance. The AD10200 uses innovative high-density circuit
design to achieve exceptional matching and performance while
still maintaining excellent isolation, and providing for significant
board area savings.
The AD10200 operates with 5.0 V supply for the analog-to-
digital conversion. Each channel is completely independent
allowing operation with independent encode and analog inputs.
The AD10200 is packaged in a 68-lead ceramic chip carrier
package. Manufacturing is done on Analog Devices, Inc. MIL-
38534 Qualified Manufacturers Line (QML) and components
are available up to Class-H (–50°C to +125°C).
PRODUCT HIGHLIGHTS
FEATURES
Dual, 105 MSPS Minimum Sample Rate
Channel-Channel Isolation, >80 dB
AC-Coupled Signal Conditioning Included
Gain Flatness up to Nyquist: < 0.2 dB
Input VSWR 1.1:1 to Nyquist
80 dB Spurious-Free Dynamic Range
Two’s Complement Output Format
3.3 V or 5 V CMOS-Compatible Output Levels
0.850 W per Channel
Industrial and Military Grade
APPLICATIONS
Radar IF Receivers
Phased Array Receivers
Communications Receivers
Secure Communications
GPS Antijamming Receivers
Multichannel, Multimode Receivers
PRODUCT DESCRIPTION
1. Guaranteed sample rate of 105 MSPS.
2. Input signal conditioning with full power bandwidth to
250 MHz.
3. Fully tested/characterized performance at 121 MHz A
IN
.
4. Optimized for IF sampling.
The AD10200 is a full channel ADC solution with on-module
signal conditioning for improved dynamic performance and
fully matched channel-to-channel performance. The module
FUNCTIONAL BLOCK DIAGRAM
A
IN
A2
7
A
IN
B2
63
D00A
34
(LSB)
D01A
33
T1A
D02A
32
D03A
31
D04A
30
D05A
29
D06A
28
D07A
25
D08A
24
D09A
23
D10A
22
D11A
21
(MSB)
TIMING
REF
REF
TIMING
OUTPUT RESISTORS
OUTPUT RESISTORS
12
ADC
12
ADC
12
12
T/H
50
50
T1B
50
D00B
(LSB)
49
D01B
48
D02B
47
D03B
46
D04B
AD10200
T/H
45
D05B
42
D06B
41
D07B
40
D08B
39
D09B
38
D10B
37
D11B
(MSB)
18
17
3
56
53
54
ENCODEA
ENCODEA
REF_A_OUT
REF_B_OUT
ENCODEB
ENCODEB
REV.
B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
©Analog Devices, Inc.,
2001–2016