AD7837/AD7847
CIRCUIT INFORMATION
D/A SECTION
A simplified circuit diagram for one of the D/A converters and
output amplifier is shown in Figure 10.
Table I. AD7847 Truth Table
CSA
CSB
WR
Function
X
1
0
1
0
g
1
g
X
1
1
0
0
1
g
g
1
X
g
g
g
0
0
0
No Data Transfer
No Data Transfer
A segmented scheme is used whereby the 2 MSBs of the 12-bit
data word are decoded to drive the three switches A-C. The
remaining 10 bits drive the switches (S0–S9) in a standard R-2R
ladder configuration.
Data Latched to DAC A
Data Latched to DAC B
Data Latched to Both DACs
Data Latched to DAC A
Data Latched to DAC B
Data Latched to Both DACs
Each of the switches A–C steers 1/4 of the total reference cur-
rent with the remaining 1/4 passing through the R-2R section.
The output amplifier and feedback resistor perform the current
to voltage conversion giving
X = Don’t Care. g = Rising Edge Triggered.
V
OUT = – D × VREF
CSA, CSB
where D is the fractional representation of the digital word. (D
t1
t2
can be set from 0 to 4095/4096.)
t3
WR
The output amplifier can maintain 10 V across a 2 kΩ load. It
is internally compensated and settles to 0.01% FSR (1/2 LSB)
in less than 5 µs. Note that on the AD7837, VOUT must be con-
t5
t4
VALID
DATA
nected externally to RFB
.
DATA
Figure 12. AD7847 Write Cycle Timing Diagram
R
R
R
V
REF
2R
C
2R
B
2R
A
2R
S9
2R
S8
2R
S0
2R
INTERFACE LOGIC INFORMATION—AD7837
R/2
The input loading structure on the AD7837 is configured for
interfacing to microprocessors with an 8-bit-wide data bus. The
part contains two 12-bit latches per DAC—an input latch and
a DAC latch. Each input latch is further subdivided into a least-
significant 8-bit latch and a most-significant 4-bit latch. Only the
data held in the DAC latches determines the outputs from the part.
The input control logic for the AD7837 is shown in Figure 13,
while the write cycle timing diagram is shown in Figure 14.
V
OUT
SHOWN FOR ALL 1s ON DAC
AGND
Figure 10. D/A Simplified Circuit Diagram
INTERFACE LOGIC INFORMATION—AD7847
The input control logic for the AD7847 is shown in Figure 11.
The part contains a 12-bit latch for each DAC. It can be treated
as two independent DACs, each with its own CS input and a com-
mon WR input. CSA and WR control the loading of data to the
DAC A latch, while CSB and WR control the loading of the
DAC B latch. The latches are edge triggered so that input data
is latched to the respective latch on the rising edge of WR. If CSA
and CSB are both low and WR is taken high, the same data will
be latched to both DAC latches. The control logic truth table is
shown in Table I, while the write cycle timing diagram for the
part is shown in Figure 12.
DAC A
LATCH
DAC B
LATCH
LDAC
CS
12
12
WR
4
DAC A MS
INPUT
LATCH
8
A0
A1
DAC A LS
INPUT
LATCH
4
DAC B LS
INPUT
LATCH
CSA
WR
8
DAC A LATCH
DAC B LS
INPUT
LATCH
DAC B LATCH
CSB
8
DB7 DB0
Figure 11. AD7847 Input Control Logic
Figure 13. AD7837 Input Control Logic
REV. C
–7–
ADI [ ADI ]
