AD811
A Video Keyer Circuit
The bias currents required at the output of the multipliers are
provided by R8 and R9. A dc-level-shifting network comprising
R10/R12 and R11/R13 ensures that the input nodes of the
AD811 are positioned at a voltage within its common-mode
range. At high frequencies C1 and C2 bypass R10 and R11
respectively. R14 is included to lower the HF loop gain, and is
needed because the voltage-to-current conversion in the
AD834s, via the Y2 inputs, results in an effective value of the
feedback resistance of 250 Ω; this is only about half the value
required for optimum flatness in the AD811’s response. (Note
that this resistance is unaffected by G: when G = 1, all the
feedback is via U1, while when G = 0 it is all via U2). R14
reduces the fractional amount of output current from the multi-
pliers into the current-summing inverting input of the AD811,
by sharing it with R8. This resistor can be used to adjust the
bandwidth and damping factor to best suit the application.
By using two AD834 multipliers, an AD811, and a 1 V dc
source, a special form of a two-input VCA circuit called a
video keyer can be assembled. “Keying” is the term used in
reference to blending two or more video sources under the
control of a third signal or signals to create such special effects
as dissolves and overlays. The circuit shown in Figure 41 is a
two-input keyer, with video inputs VA and VB, and a control
input VG. The transfer function (with VOUT at the load) is
given by:
VOUT = G VA + (1–G) VB
where G is a dimensionless variable (actually, just the gain of
the “A” signal path) that ranges from 0 when VG = 0, to 1
when VG = +1 V. Thus, VOUT varies continuously between VA
and VB as G varies from 0 to 1.
Circuit operation is straightforward. Consider first the signal
path through U1, which handles video input VA. Its gain is
clearly zero when VG = 0 and the scaling we have chosen
ensures that it is unity when VG = +1 V; this takes care of the
first term of the transfer function. On the other hand, the VG
input to U2 is taken to the inverting input X2 while X1 is
biased at an accurate +1 V. Thus, when VG = 0, the response
to video input VB is already at its full-scale value of unity,
whereas when VG = +1 V, the differential input X1–X2 is zero.
This generates the second term.
To generate the 1 V dc needed for the “1–G” term an AD589
reference supplies 1.225 V ± 25 mV to a voltage divider consist-
ing of resistors R2 through R4. Potentiometer R3 should be
adjusted to provide exactly +1 V at the X1 input.
In this case, we have shown an arrangement using dual supplies
of ±5 V for both the AD834 and the AD811. Also, the overall
gain in this case is arranged to be unity at the load, when it is
driven from a reverse-terminated 75 Ω line. This means that the
“dual VCA” has to operate at a maximum gain of 2, rather
C1
+5V
R7
R14
0.1F
SETUP FOR DRIVING
REVERSE-TERMINATED LOAD
SEE TEXT
45.3⍀
R10
2.49k⍀
Z
V
OUT
O
R5
TO PIN 6
AD811
113⍀
V
R6
226⍀
G
Z
200⍀
200⍀
O
(0 TO +1V dc)
TO Y2
8
7
6
5
X2
X1 +V
W1
S
+5V
R1
INSET
R8
29.4⍀
U1
AD834
R12
6.98k⍀
U4
1.87k⍀
AD589
+5V
Y1 Y2 –V
W2
4
S
R2
174⍀
2
1
3
V
A
FB
C3
0.1F
(؎1V FS)
–5V
–5V
+5V
R3
100⍀
LOAD
GND
U3
AD811
R9
29.4⍀
R13
6.98k⍀
8
7
6
5
V
OUT
R4
1.02k⍀
X2
W1
X1 +V
S
C4
0.1F
C2
0.1F
U1
AD834
Y1 Y2 –V
W2
4
S
LOAD
GND
FB
2
1
3
R11
2.49k⍀
V
B
–5V
–5V
(؎1V FS)
Figure 41. A Practical Video Keyer Circuit
REV. D
–13–
ADI [ ADI ]
