AD674B/AD774B
VALUE OF A AT LAST CONVERT COMMAND
0
Q
D
EOC 12
EOC 8
D
EN
EN
START CONVERT
R
S
Q
SAR
RESET
S
R
Q
QB
CE
HIGH IF CONVERSION
IN PROGRESS
CS
CLK EN
STATUS
R/C
NYBBLE A
ENABLE
A
0
NYBBLE B
ENABLE
READ
TO
OUTPUT
BUFFERS
NYBBLE C
ENABLE
12/8
NYBBLE = 0
ENABLE
Figure 9. Equivalent Internal Logic Circuitry
CONTROL LOGIC
Table I. Truth Table
The AD674B and AD774B contain on-chip logic to provide
conversion initiation and data read operations from signals
commonly available in microprocessor systems; this internal
logic circuitry is shown in Figure 9.
CE CS R/C 12/8 A0 Operation
0
X
1
1
1
1
1
X
1
0
0
0
0
0
X
X
0
0
1
X
X
X
X
1
X
X
0
1
X
0
None
None
The control signals CE, CS, and R/C control the operation of
the converter. The state of R/C when CE and CS are both
asserted determines whether a data read (R/C = 1) or a convert
(R/C = 0) is in progress. The register control inputs, A0 and
12/8, control conversion length and data format. If a conversion
is started with A0 low, a full 12-bit conversion cycle is initiated.
If A0 is high during a convert start, a shorter 8-bit conversion
cycle results. During data read operations, A0 determines
whether the three-state buffers containing the 8 MSBs of the
conversion result (A0 = 0) or the 4 LSBs (A0 = 1) are enabled.
The 12/8 pin determines whether the output data is to be orga-
nized as two 8-bit words (12/8 tied to DIGITAL COMMON)
or a single 12-bit word (12/8 tied to VLOGIC). In the 8-bit mode,
the byte addressed when A0 is high contains the 4 LSBs from
the conversion followed by four trailing zeroes. This organiza-
tion allows the data lines to be overlapped for direct interface to
8-bit buses without the need for external three-state buffers.
Initiate 12-Bit Conversion
Initiate 8-Bit Conversion
Enable 12-Bit Parallel Output
Enable 8 Most Significant Bits
Enable 4 LSBs + 4 Trailing Zeroes
1
1
0
0
1
The ADC may be operated in one of two modes, the full-control
mode and the standalone mode. The full-control mode uses all
the control signals and is useful in systems that address decode
multiple devices on a single data bus. The standalone mode is
useful in systems with dedicated input ports available. In gen-
eral, the standalone mode is capable of issuing start-convert
commands on a more precise basis and therefore produces
higher accuracy results. The following sections describe these
two modes in more detail.
FULL-CONTROL MODE
Chip Enable (CE), Chip Select (CS), and Read/Convert (R/C)
are used to control Convert or Read modes of operation. Either
CE or CS may be used to initiate a conversion. The state of R/C
when CE and CS are both asserted determines whether a data
Read (R/C = 1) or a Convert (R/C = 0) is in progress. R/C
should be LOW before both CE and CS are asserted; if R/C is
HIGH, a Read operation will momentarily occur, possibly
resulting in system bus contention.
An output signal, STS, indicates the status of the converter.
STS goes high at the beginning of a conversion and returns low
when the conversion cycle is complete.
REV. C
–9–
ADI [ ADI ]
