AD7242/AD7244
AD7242/AD7244 PIN FUNCTION DESCRIPTION
Description
DIP
Pin No.
Mnemonic
1
LDACA
Load DAC, Logic Input. A new word is transferred into DAC Latch A from input Latch A on the fall-
ing edge of this signal. If LDACA is hard-wired low, data is transferred from input Latch A to DAC
Latch A on the sixteenth falling edge of TCLKA after TFSA goes low.
2
3
4
TFSA
DTA
Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for DACA
data with serial data expected after the falling edge of this signal.
Transmit Data, Logic Input. This is the data input which is used in conjunction with TFSA and
TCLKA to transfer serial data to input Latch A.
TCLKA
Transmit Clock, Logic Input. Serial data bits for DACA are latched on the falling edge of TCLKA
when TFSA is low.
5
6
7
8
9
DGND
TP1
Digital Ground. Both DGND pins for the device must be tied together at the device.
Test Pin 1. Used when testing the device. Do not connect anything to this pin.
VDD
Positive Power Supply, 5 V ± 5%. Both VDD pins for the device must be tied together at the device.
Analog Ground. Both AGND pins for the device must be tied together at the device.
AGND
VOUTB
Analog Output Voltage from DACB. This output comes from a buffer amplifier. The range is bipolar,
±3 V with REF INB = +3 V.
10
11
12
VSS
Negative Power Supply, –5 V ± 5%. Both VSS pins for the device must be tied together at the device.
TP2
Test Pin 2. Used when testing the device. Do not connect anything to this pin.
REF INB
DACB Voltage Reference Input. The voltage reference for DACB is applied to this pin. It is internally
buffered before being applied to DACB. The nominal reference voltage for correct operation of the
AD7242/AD7244 is 3 V.
13
LDACB
Load DAC, Logic Input. A new word is transferred into DAC Latch B from input Latch B on the fall-
ing edge of this signal. If LDACB is hard-wired low, data is transferred from input Latch B to DAC
Latch B on the sixteenth falling edge of TCLKB after TFSB goes low.
14
15
16
TFSB
DTB
Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for DACB
data with serial data expected after the falling edge of this signal.
Transmit Data, Logic Input. This is the data input used in conjunction with TFSB and TCLKB to
transfer serial data to input Latch B.
TCLKB
Transmit Clock, Logic Input. Serial data bits for DACB are latched on the falling edge of TCLKB
when TFSB is low.
17
18
19
20
21
DGND
TP3
Digital Ground. Both DGND pins for the device must be tied together at the device.
Test Pin 3. Used when testing the device. Do not connect anything to this pin.
VDD
Positive Power Supply, 5 V ± 5%. Both VDD pins for the device must be tied together at the device.
Analog Ground. Both AGND pins for the device must be tied together at the device.
AGND
VOUTA
Analog Output Voltage from DACA. This output comes from a buffer amplifier. The range is bipolar,
±3 V with REF INA = +3 V.
22
23
VSS
Negative Power Supply, –5 V ± 5%. Both VSS pins for the device must be tied together at the device.
REF OUT
Voltage Reference Output. To operate the DACs with this internal reference, REF OUT should be
connected to both REF INA and REF INB. The external load capability of the reference is 500 µA.
24
REF INA
DACA Voltage Reference Input. The voltage reference for DACA is applied to this pin. It is internally
buffered before being applied to DACA. The nominal reference voltage for correct operation of the
AD7242/AD7244 is 3 V.
REV. A
–5–
ADI [ ADI ]
