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5962-8980501IA 参数 Datasheet PDF下载

5962-8980501IA图片预览
型号: 5962-8980501IA
PDF下载: 下载PDF文件 查看货源
内容描述: 集成电路真RMS至DC转换器 [Integrated Circuit True RMS-to-DC Converter]
分类和应用: 转换器
文件页数/大小: 8 页 / 152 K
品牌: ADI [ ADI ]
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AD536A  
The two-pole post-filter uses an active filter stage to provide  
even greater ripple reduction without substantially increasing  
the settling times over a circuit with a one-pole filter. The values  
of CAV, C2, and C3 can then be reduced to allow extremely fast  
settling times for a constant amount of ripple. Caution should  
be exercised in choosing the value of CAV, since the dc error is  
dependent upon this value and is independent of the post filter.  
factors, (such as low duty cycle pulse trains), the averaging time  
constant should be at least ten times the signal period. For  
example, a 100 Hz pulse rate requires a 100 ms time constant,  
which corresponds to a 4 µF capacitor (time constant = 25 ms  
per µF).  
The primary disadvantage in using a large CAV to remove ripple  
is that the settling time for a step change in input level is in-  
creased proportionately. Figure 5 shows that the relationship  
between CAV and 1% settling time is 115 milliseconds for each  
microfarad of CAV. The settling time is twice as great for de-  
creasing signals as for increasing signals (the values in Figure 5  
are for decreasing signals). Settling time also increases for low  
signal levels, as shown in Figure 6.  
For a more detailed explanation of these topics refer to the  
RMS to DC Conversion Application Guide 2nd Edition, available  
from Analog Devices.  
C3  
C2  
C3  
Figure 7. 2-Pole PostFilter  
Figure 5. Error/Settling Time Graph for Use with the Stan-  
dard rms Connection in Figure 1  
Figure 6. Settling Time vs. Input Level  
Figure 8. Performance Features of Various Filter Types  
A better method for reducing output ripple is the use of a  
post-filter.Figure 7 shows a suggested circuit. If a single-pole  
filter is used (C3 removed, RX shorted), and C2 is approximately  
twice the value of CAV, the ripple is reduced as shown in Figure  
8 and settling time is increased. For example, with CAV = 1 µF  
and C2 = 2.2 µF, the ripple for a 60 Hz input is reduced from  
10% of reading to approximately 0.3% of reading. The settling  
time, however, is increased by approximately a factor of 3. The  
values of CAV and C2, can, therefore, be reduced to permit faster  
settling times while still providing substantial ripple reduction.  
AD536A PRINCIPLE OF OPERATION  
The AD536A embodies an implicit solution of the rms equation  
that overcomes the dynamic range as well as other limitations  
inherent in a straightforward computation of rms. The actual  
computation performed by the AD536A follows the equation:  
2
VIN  
V rms = Avg.  
V rms   
REV. B  
5–