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5962-8971001XA 参数 Datasheet PDF下载

5962-8971001XA图片预览
型号: 5962-8971001XA
PDF下载: 下载PDF文件 查看货源
内容描述: 锁存CMOS 8位/ 16通道模拟多路复用器 [CMOS Latched 8-/16-Channel Analog Multiplexers]
分类和应用: 复用器开关复用器或开关信号电路
文件页数/大小: 20 页 / 415 K
品牌: ADI [ ADI ]
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ADG526A/ADG527A  
SPECIFICATIONS  
DUAL SUPPLY  
VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V, unless otherwise noted.  
Table 1.  
ADG526A/ADG527A  
ADG526A  
T Version  
K Version  
B Version  
Parameter  
25°C −40°C to +85°C 25°C −40°C to +85°C 25°C −55°C to +125°C Unit  
Comments  
ANALOG SWITCH  
Analog Signal Range  
VSS  
VDD  
280  
VSS  
VDD  
VSS  
VDD  
280  
VSS  
VDD  
VSS  
VDD  
280  
VSS  
VDD  
V min  
V max  
Ω typ  
RON  
−10 V ≤ VS ≤ +10 V, IDS = 1 mA;  
see Figure 15  
450  
300  
600  
400  
450 600  
300 400  
450 600  
Ω max  
Ω max  
VDD = +15 V ( 10ꢀ%,  
VSS = −15 V ( 10ꢀ%  
300 400  
Ω max  
VDD = +15 V ( 5ꢀ%,  
VSS = −15 V ( 5ꢀ%  
RON Drift  
RON Match  
0.6  
5
0.6  
5
0.6  
5
ꢀ/°C typ −10 V ≤ VS ≤ +10 V, IDS = 1 mA  
ꢀ typ  
−10 V ≤ VS ≤ +10 V, IDS = 1 mA  
IS (Off%, Off Input Leakage 0.02  
0.02  
0.02  
nA typ  
V1 = 10 V, V2 = 10 V;  
see Figure 16  
1
0.04  
50  
1
0.04  
50  
1
0.04  
50  
nA max  
nA typ  
ID (Off%, Off Output  
Leakage  
V1 = 10 V, V2 = 10 V;  
see Figure 17  
ADG526A  
ADG527A  
ID (On%, On Channel  
Leakage  
ADG526A  
ADG527A  
IDIFF, Differential Off  
Output Leakage  
1
1
0.04  
200  
100  
1
1
0.04  
200  
100  
1
200  
nA max  
nA max  
nA typ  
0.04  
1
V1 = 10 V, V2 = 10 V;  
see Figure 18  
1
1
200  
100  
25  
1
1
200  
100  
25  
200  
nA max  
nA max  
nA max  
V1 = 10 V, V2 = 10 V;  
see Figure 19  
(ADG527A Only%  
DIGITAL CONTROL  
VINH, Input High Voltage  
VINL, Input Low Voltage  
IINL or IINH  
2.4  
0.8  
1
2.4  
0.8  
1
2.4  
0.8  
1
V min  
V max  
μA max  
pF max  
VIN = 0 to VDD  
CIN, Digital Input  
Capacitance  
8
8
8
DYNAMIC  
CHARACTERISTICS1  
tTRANSITION  
200  
200  
200  
ns typ  
V1 = 10 V, V2 = 10 V;  
see Figure 20  
300  
50  
25  
200  
300  
200  
300  
100  
400  
10  
300 400  
50  
300 400  
50  
ns max  
ns typ  
ns min  
ns typ  
ns max  
ns typ  
ns max  
ns min  
ns min  
tOPEN  
See Figure 21  
25  
10  
25  
10  
WR  
200  
200  
See Figure 22 and Figure 23  
See Figure 22 and Figure 24  
tON (EN,  
tOFF (EN,  
%
400  
300 400  
200  
300 400  
200  
RS  
%
400  
120  
100  
300 400  
100 120  
100  
300 400  
100 130  
100  
tW , Write Pulse Width  
tS, Address Enable Setup  
Time  
See Figure 13  
See Figure 13  
tH, Address Enable Hold  
Time  
tRS, Reset Pulse Width  
10  
10  
10  
ns min  
ns min  
See Figure 13  
See Figure 14  
100  
100  
100  
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