AD7846
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
DB2
DB1
DB0
DB3
DB4
DB5
1
28
27
26
25
24
23
22
21
4
3
2
1
28 27 26
2
PIN 1
IDENTIFIER
3
V
5
6
7
8
9
25
24
23
22
21
LDAC
CLR
CS
OUT
R
V
4
IN
LDAC
CLR
CS
DD
V
V
5
REF+
REF–
V
OUT
AD7846
TOP VIEW
(Not to Scale)
R/W
6
R
IN
AD7846
TOP VIEW
(Not to Scale)
V
V
SS
CC
7
V
V
R/W
REF+
DB15 10
DB14 11
20 DGND
19 DB6
8
V
REF–
CC
9
V
20 DGND
SS
10
11
12
13
14
19
DB15
DB14
DB13
DB12
DB11
DB6
12 13 14 15 16 17 18
18
DB7
17
DB8
16
DB9
15
DB10
Figure 7. PDIP Pin Configuration
Figure 8. CERDIP Pin Configuration
Table 5. Pin Function Descriptions
Pin
Mnemonic
DB2 to DB0
VDD
VOUT
RIN
Description
1 to 3
Data I/Os. DB0 is LSB.
Positive Supply for Analog Circuitry. This is +15 V nominal.
DAC Output Voltage.
Input to Summing Resistor of DAC Output Amplifier. This is used to select output voltage ranges. See Table 6.
VREF+ Input. The DAC is specified for VREF+ = +5 V.
VREF− Input. For unipolar operation connect VREF− to 0 V, and for bipolar operation connect it to −5 V. The device is
specified for both conditions.
4
5
6
7
±
VREF+
VREF−
9
VSS
Negative Supply for the Analog Circuitry. This is −15 V nominal.
10 to 19 DB15 to DB6 Data I/Os. DB15 is MSB.
20
21
22
23
24
25
DGND
VCC
R/W
CS
Ground for Digital Circuitry.
Positive Supply for Digital Circuitry. This is +5 V nominal.
R/W Input. This pin can be used to load data to the DAC or to read back the DAC latch contents.
Chip Select Input. This pin selects the device.
Clear Input. The DAC can be cleared to 000…000 or 100…000. See Table 7.
Asynchronous Load Input to DAC.
CLR
LDAC
26 to 2± DB5 to DB3
Data I/Os.
Table 6. Output Voltage Ranges
Output Range
0 V to +5 V
0 V to +10 V
+5 V to −5 V
VREF+
+5 V
+5 V
+5 V
+5 V
+5 V
VREF−
0 V
0 V
−5 V
0 V
−5 V
RIN
VOUT
0 V
VOUT
+5 V
0 V
+5 V to −5 V
+10 V to −10 V
Rev. G | Page 7 of 24
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