OP490
(@ V = ؎1.5 V to ؎15 V, T = 25؇C, unless otherwise noted)
WAFER TEST LIMITS
Parameter
S
A
Symbol
Conditions
Limits
Unit
Input Offset Voltage
Input Offset Current
Input Bias Current
VOS
IOS
IB
0.75
5
20
mV max
nA max
nA max
VCM = 0 V
VCM = 0 V
Large Signal Voltage Gain
AVO
VS = ±15 V, VO = ±10 V,
RL = 100 kW
500
250
125
V/mV min
V/mV min
V/mV min
RL = 10 kW
V+ = 5 V, V– = 0 V
1 V < VO < 4 V, RL = 100 kW
V+ = 5 V, V– = 0 V
VS = ±15 V*
Input Voltage Range
Output Voltage Swing
IVR
VO
0/4
–15/+13.5
V min
V min
VS = ±15 V
RL = 10 kW
±13.5
±10.5
4.0
V min
V min
V min
mV max
RL = 2 kW
VOH
VOL
V+ = 5 V, V– = 0 V, RL = 2 kW
V+ = 5 V, V– = 0 V, RL = 10 kW
500
Common-Mode Rejection Ratio
CMRR
V+ = 5 V, V– = 0 V, 0 V < VCM < 4 V
VS = ±15 V, –15 V < VCM < +13.5 V
80
90
dB min
dB min
Power Supply Rejection Ratio
Supply Current (All Amplifiers)
PSRR
ISY
10
80
mV/V max
mA max
VS = ±15 V, No Load
NOTE
*Guaranteed by CMRR test.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
V+
+IN
OUTPUT
–IN
V–
Figure 1. Simplified Schematic
–4–
REV. C
ADI [ ADI ]
