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5962-8964501PA 参数 Datasheet PDF下载

5962-8964501PA图片预览
型号: 5962-8964501PA
PDF下载: 下载PDF文件 查看货源
内容描述: 精密, 16 MHz的CBFET运算放大器 [Precision, 16 MHz CBFET Op Amp]
分类和应用: 运算放大器放大器电路
文件页数/大小: 8 页 / 237 K
品牌: ADI [ ADI ]
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AD845  
MEASURING AD 845 SETTLING TIME  
and stable, accurately defined gain. Low input bias currents and  
fast settling are achieved with the FET input AD845.  
T he Figure 24 shows the AD845 settling time performance.  
T his measurement was accomplished by driving the amplifier  
in the unity-gain inverting mode with a fast pulse generator.  
T he input summing junction was measured using false nulling  
techniques.  
Most monolithic instrumentation amplifiers do not have the  
high frequency performance of the circuit in Figure 26. T he cir-  
cuit bandwidth is 10.9 MHz at a gain of 1 and 8.8 MHz at a  
gain of 10; settling time for the entire circuit is 900 ns to 0.01%  
for a 10 V step (Gain = 10).  
Settling time is defined as:  
T he interval of time from the application of an ideal  
step function input until the closed-loop amplifier output  
has entered and remains within a specified error band.  
T he capacitors employed in this circuit greatly improve the  
amplifier’s settling time and phase margin.  
Components of settling time include:  
1. Propagation time through the amplifier  
2. Slewing time to approach the final output value  
3. Recovery time from overload associated with the slewing  
4. Linear settling to within a specified error band.  
T hese individual components can easily be seen in Figure 24.  
Settling time is extremely important in high speed applications  
where the current output of a DAC must be converted to a  
voltage. When driving a 500 load in parallel with a 100 pF  
capacitor, the AD845 settles to 0.1% in 250 ns and to 0.01% in  
310 ns.  
Figure 26. High Perform ance, High Speed Instrum enta-  
tion Am plifier  
Table I. P erform ance Sum m ary for the Three O p Am p  
Instrum entation Am plifier Circuit  
3 O p-Am p In-Am p  
Sm all Signal  
Bandwidth  
Settling Tim e  
to 0.01%  
Gain  
RG  
Figure 24. Settling Characteristics 0 V to 10 V Step  
Upper Trace: Output of AD845 Under Test (5 V/Div)  
Lower Trace: Error Voltage (1 m V/Div)  
1
2
10  
100  
Open  
2k  
226 Ω  
20 Ω  
10.9 MHz  
8.8 MHz  
2.6 MHz  
290 kHz  
500 ns  
500 ns  
900 ns  
7.5 µs  
Note: Resistors around the amplifiers’ input pins need to be small enough in  
value so that the RC time constant they form, with stray circuit capacitance,  
does not reduce circuit bandwidth.  
Figure 25. Settling Tim e Test Circuit  
A H IGH SP EED INSTRUMENTATIO N AMP  
Figure 27. The Pulse Response of the Three Op Am p  
Instrum entation Am plifier. Gain = 1, Horizontal Scale:  
0.5 m s/Div; Vertical Scale: 5 V/Div  
T he three op amp instrumentation amplifier circuit shown in  
Figure 26 can provide a range of gains from unity up to 1000  
and higher. T he instrumentation amplifier configuration fea-  
tures high common-mode rejection, balanced differential inputs  
REV. D  
–7–