AD524
As RG is reduced to increase the programmed gain, the trans-
conductance of the input preamp increases to the transconduct-
ance of the input transistors. This has three important advantages.
First, this approach allows the circuit to achieve a very high
open loop gain of 3 × 108 at a programmed gain of 1000, thus
reducing gain-related errors to a negligible 30 ppm. Second, the
gain bandwidth product, which is determined by C3 or C4 and
the input transconductance, reaches 25 MHz. Third, the input
voltage noise reduces to a value determined by the collector
current of the input transistors for an RTI noise of 7 nV/√Hz at
G = 1000.
10k⍀
0.01%
10k⍀
0.1%
1k⍀
10T
INPUT
20V p-p
V
OUT
100k⍀
0.1%
+V
S
RG
1
G = 10
G = 100
AD524
11k⍀
0.1%
100⍀
0.1%
1k⍀
0.1%
G = 1000
RG
2
–V
S
Figure 27. Settling Time Test Circuit
INPUT PROTECTION
As interface amplifiers for data acquisition systems, instrumen-
tation amplifiers are often subjected to input overloads, i.e.,
voltage levels in excess of the full scale for the selected gain
range. At low gains, 10 or less, the gain resistor acts as a current
limiting element in series with the inputs. At high gains the
lower value of RG will not adequately protect the inputs from
excessive currents. Standard practice would be to place series
limiting resistors in each input, but to limit input current to
below 5 mA with a full differential overload (36 V) would re-
quire over 7k of resistance which would add 10 nV√Hz of noise.
To provide both input protection and low noise a special series
protect FET was used.
+V
S
I
I
2
1
V
B
50A
50A
R52
A1
A2
C4
20k⍀
SENSE
R53
C3
20k⍀
A3
V
R57
20k⍀
O
CH ,
2
R56
20k⍀
R54
20k⍀
CH , CH
3
4
R55
20k⍀
Q1, Q3
Q2, Q4
–IN
4.44k⍀
REFERENCE
+IN
CH
1
CH , CH ,
2
CH
3
RG
RG
2
1
404⍀
40⍀
4
A unique FET design was used to provide a bidirectional cur-
rent limit, thereby, protecting against both positive and negative
overloads. Under nonoverload conditions, three channels CH2,
CH3, CH4, act as a resistance (≈1 kΩ) in series with the input as
before. During an overload in the positive direction, a fourth
channel, CH1, acts as a small resistance (≈3 kΩ) in series with
the gate, which draws only the leakage current, and the FET
limits IDSS. When the FET enhances under a negative overload,
the gate current must go through the small FET formed by CH1
and when this FET goes into saturation, the gate current is
limited and the main FET will go into controlled enhancement.
The bidirectional limiting holds the maximum input current to
3 mA over the 36 V range.
G100
G1000
I
3
I
4
50A
CH
50A
1
–V
S
Figure 28 Simplified Circuit of Amplifier; Gain Is Defined as
((R56 + R57)/(RG)) + 1. For a Gain of 1, RG Is an Open Circuit
Theory of Operation
The AD524 is a monolithic instrumentation amplifier based on
the classic 3 op amp circuit. The advantage of monolithic con-
struction is the closely matched components that enhance the
performance of the input preamp. The preamp section develops
the programmed gain by the use of feedback concepts. The
programmed gain is developed by varying the value of RG (smaller
values increase the gain) while the feedback forces the collector
currents Q1, Q2, Q3 and Q4 to be constant, which impresses
the input voltage across RG.
INPUT OFFSET AND OUTPUT OFFSET
Voltage offset specifications are often considered a figure of
merit for instrumentation amplifiers. While initial offset may be
adjusted to zero, shifts in offset voltage due to temperature
variations will cause errors. Intelligent systems can often correct
for this factor with an autozero cycle, but there are many small-
signal high-gain applications that don’t have this capability.
+V
S
AD712
+V
s
10
16.2k⍀
100
AD524
1F
DUT
1000
1/2
RG
2
1/2
1F
9.09k⍀
1k⍀
1F
16.2k⍀
1.82k⍀
G1, 10, 100
G1000
–V
–V
S
S
100⍀
1.62M⍀
Figure 29. Noise Test Circuit
–8–
REV. E
ADI [ ADI ]
