AD524
TABLE OF CONTENTS
Features .............................................................................................. 1
Input Offset and Output Offset................................................ 15
Gain.............................................................................................. 16
Input Bias Currents.................................................................... 17
Common-Mode Rejection........................................................ 17
Grounding................................................................................... 18
Sense Terminal............................................................................ 18
Reference Terminal .................................................................... 18
Programmable Gain................................................................... 20
Autozero Circuits ....................................................................... 20
Error Budget Analysis................................................................ 21
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 25
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 8
Connection Diagrams.................................................................. 8
ESD Caution.................................................................................. 8
Typical Performance Characteristics ............................................. 9
Test Circuits................................................................................. 14
Theory of Operation ...................................................................... 15
Input Protection.......................................................................... 15
REVISION HISTORY
11/07—Rev. E to Rev. F
Updated Format..................................................................Universal
Changes to General Description .................................................... 1
Changes to Figure 1.......................................................................... 1
Changes to Figure 3 and Figure 4 Captions .................................. 8
Changes to Error Budget Analysis Section ................................. 21
Changes to Ordering Guide .......................................................... 25
4/99—Rev. D to Rev. E
Rev. F | Page 2 of 28
ADI [ ADI ]
