AD558
OUTPUT
AMP
ADDRESS BUS
0.5mA
16
16
15
14
13
V
16
OUT
–V
ADDRESS SELECT
PULSE LOGIC
V
SENSE
OUT
8080A
V
SELECT
V
OUT
CS
CE
OUT
AD558
MEMW
AGND
DB0–DB7
8
8
b. 0 V to 10 V Output Range
Figure 11. Offset Connection Diagrams
DATA BUS
INTERFACING THE AD558 TO MICROPROCESSOR
DATA BUSES
MEMW → CE
DECODED ADDRESS SELECT PULSE → CS
The AD558 is configured to act like a “write only” location in
memory that may be made to coincide with a read only memory
location or with a RAM location. The latter case allows data
previously written into the DAC to be read back later via the
RAM. Address decoding is partially complete for either ROM
or RAM. Figure 12 shows interfaces for three popular micropro-
cessor systems.
b. 8080A/AD558 Interface
8
ADDRESS BUS
8
MA 0 – 7
TPA
ADDRESS
LATCH
&
CS
CE
V
OUT
1802
AD558
ADDRESS BUS
DECODE
MWR
16
16
DB0–DB7
ADDRESS
DECODER
6800
8
8
VMA
V
OUT
DATA BUS
CDP 1802: MWR → CE
CS
CE
AD558
φ2
DECODED ADDRESS SELECT PULSE → CS
R/W
DB0–DB7
8
c. 1802/AD558 Interface
Figure 12. Interfacing the AD558 to Microprocessors
8
DATA BUS
R/W → CE
GATED DECODED ADDRESS → CS
a. 6800/AD558 Interface
Performance (typical @ +25؇C, VCC ؎ +5 V to +15 V unless otherwise noted)
LSB
1.75
1.50
1.25
1.00
0.75
0.50
0.25
LSB
1/2
ALL AD558
AD558S, T
ALL AD558
AD558S, T
ZERO
ERROR
1/4
FULL
SCALE
ERROR
0
0
o
–0.25
–0.50
–0.75
–1.00
C
–55
–25
0
+25
+50
+75 +100 +125
–1/4
–1/2
1LSB = 0.39% OF FULL SCALE
o
C
–55
–25
0
+25
+50
+75 +100 +125
1LSB = 0.39% OF FULL SCALE
Figure 13. Full-Scale Accuracy vs. Temperature
Performance of AD558
Figure 14. Zero Drift vs. Temperature Performance
of AD558
REV. A
–7–
ADI [ ADI ]
