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5962-8763501RA 参数 Datasheet PDF下载

5962-8763501RA图片预览
型号: 5962-8763501RA
PDF下载: 下载PDF文件 查看货源
内容描述: [8-Bit Signal Conditioning ADC.]
分类和应用: 转换器
文件页数/大小: 12 页 / 362 K
品牌: ADI [ ADI ]
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AD670  
6b. Bipolar  
Figure 7. Control Logic Block Diagram  
Table II. AD670 Control Signal Truth Table  
R/W  
CS  
CE  
OPERATION  
0
1
0
0
0
0
WRITE/CONVERT  
READ  
X
X
X
1
1
X
NONE  
NONE  
6c. Full Scale (Unipolar)  
Figure 6. Transfer Curves  
Timing  
The AD670 is easily interfaced to a variety of microprocessors  
and other digital systems. The following discussion of the timing  
requirements of the AD670 control signals will provide the de-  
signer with useful insight into the operation of the device.  
CONTROL AND TIMING OF THE AD670  
Control Logic  
The AD670 contains on-chip logic to provide conversion and  
data read operations from signals commonly available in micro-  
processor systems. Figure 7 shows the internal logic circuitry of  
the AD670. The control signals, CE, CS, and R/W control the  
operation of the converter. The read or write function is deter-  
mined by R/W when both CS and CE are low as shown in  
Table II. If all three control inputs are held low longer than the  
conversion time, the device will continuously convert until one  
input, CE, CS, or R/W is brought high. The relative timing of  
these signals is discussed later in this section.  
Write/Convert Start Cycle  
Figure 8 shows a complete timing diagram for the write/convert  
start cycle. CS (chip select) and CE (chip enable) are active low  
and are interchangeable signals. Both CS and CE must be low  
for the converter to read or start a conversion. The minimum  
pulse width, tW, on either CS or CE is 300 ns to start a  
conversion.  
Table III. AD670 TIMING SPECIFICATIONS  
@ +25؇C  
Symbol  
Parameter  
Min  
Typ  
Max  
Units  
WRITE/CONVERT START MODE  
tW  
Write/Start Pulse Width  
Input Data Setup Time  
Input Data Hold  
Read/Write Setup Before Control  
Delay to Convert Start  
Conversion Time  
300  
200  
10  
ns  
ns  
ns  
ns  
ns  
µs  
tDS  
tDH  
tRWC  
tDC  
tC  
0
700  
10  
READ MODE  
tR  
Read Time  
Delay from Status Low to Data Read  
Bus Access Time  
Data Hold Time  
Output Float Delay  
250  
ns  
ns  
ns  
ns  
ns  
ns  
tSD  
tTD  
tDH  
tDT  
tRT  
250  
250  
200  
25  
0
150  
R/W before CE or CS low  
Boldface indicates parameters tested 100% unless otherwise noted. See Specifications page for explanation.  
REV. A  
–7–