AD7533
OPERATION
UNIPOLAR BINARY CODE
BIPOLAR (OFFSET BINARY) CODE
Table 5. Unipolar Binary Operation
(4-Quadrant Multiplication)
Table 4. Unipolar Binary Operation
(2-Quadrant Multiplication)
Digital Input
Digital Input
Analog Output
Analog Output
MSB
LSB
(VOUT as shown in Figure 12)
MSB
LSB
(VOUT as shown in Figure 11)
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0 1
1 0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0
511
1023
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
+VREF
+VREF
−VREF
−VREF
−VREF
−VREF
−VREF
−VREF
512
1024
1 0 0 0 0 0 0 0 0 1
1
513
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
512
1024
1 0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 1
0
512
V
REF
⎛
⎜
⎝
⎞
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎠
=
1
1024
2
⎛
⎜
⎝
⎞
⎟
⎠
−VREF
−VREF
−VREF
512
511
⎛
⎜
⎝
⎞
⎟
⎠
0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 0
511
512
1024
⎛
⎜
⎝
⎞
⎟
⎠
1
⎛
⎜
⎝
⎞
⎟
⎠
512
512
1024
⎛
⎜
⎝
⎞
⎟
⎠
0
⎛
⎜
⎝
⎞
⎟
⎠
= 0
1024
Nominal LSB magnitude for the circuit of Figure 12 is given by
Nominal LSB magnitude for the circuit of Figure 11 is given by
1
512
⎛
⎜
⎝
⎞
⎟
⎠
LSB = VREF
1
⎛
⎜
⎝
⎞
⎟
⎠
LSB = VREF
1024
BIPOLAR
ANALOG INPUT
V
±10V
DD
BIPOLAR
ANALOG INPUT
±10V
V
R1
R4
DD
1kΩ
20kΩ
R2
R5
20kΩ
V
REF
330Ω
15
14
R1
16
MSB
LSB
C1
I
1
1kΩ
R3
10kΩ
4
OUT
R2
1
2
BIPOLAR
DIGITAL
INPUT
V
REF
R
A1
330Ω
AD7533
15
14
FB
16
A2
V
OUT
13
MSB
I
2
OUT
C1
I
I
1
4
OUT
1
2
3
UNIPOLAR
DIGITAL
INPUT
R6
5kΩ
V
AD7533
OUT
LSB
13
2
OUT
GND
3
NOTES
1. R3, R4, AND R5 SELECTED FOR MATCHING AND TRACKING.
2. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
3. C1 PHASE COMPENSATION (5pF TO 15pF) MAY BE REQUIRED
WHEN USING HIGH SPEED AMPLIFIERS.
GND
NOTES
Figure 12. Bipolar Operation (4-Quadrant Multiplication)
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (5pF TO 15pF) MAY BE REQUIRED
WHEN USING HIGH SPEED AMPLIFIER.
Figure 11. Unipolar Binary Operation (2-Quadrant Multiplication)
Rev. C | Page 8 of 12
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