ADDAC80/ADDAC85/ADDAC87–SPECIFICATIONS (continued)
ADDAC85LD
Min Typ Max
ADDAC85MIL
Min Typ Max
ADDAC87
Typ
Model
Min
Max
Unit
POWER SUPPLY REQUIREMENTS
Rated Voltages
Range
15, 5
15, 5
15, 5
V
Analog Supplies
Logic Supplies
Supply Drain7
+15 V
14.5
+4.5
15.5
15.5
14.5
+4.5
15.5
+15.5
13.5
+4.5
16.5
16.5
V
V
15
25
15
20
30
20
15
25
15
20
30
20
10
20
10
20
35
20
mA
mA
mA
–15 V
+5 V8
TEMPERATURE RANGE
Specification
Operating
–25
–55
–55
+85
+125
+125
–55
–55
–55
+125
+125
+125
–55
–55
–65
+125
+125
+150
°C
°C
Storage
°
C
NOTES
1Least Significant Bit.
2Adjustable to zero with external trim potentiometer.
3FSR means “Full-Scale Range” and is 20 V for the 10 V range and 10 V for the 5 V range.
4Gain and offset errors adjusted to zero at 25°C.
5CF = 0, see Figure 3a.
6Maximum with no degradation of specification, must be a constant load.
7Including 5 mA load.
85 V supply required only for CCD versions.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS
+VS to Power Ground . . . . . . . . . . . . . . . . . . . . 0 V to +18 V
–VS to Power Ground . . . . . . . . . . . . . . . . . . . . 0 V to –18 V
Digital Inputs (Pins 1 to 12) to Power Ground . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.0 V to +7 V
Ref In to Reference Ground . . . . . . . . . . . . . . . . . . . . .
Bipolar Offset to Reference Ground . . . . . . . . . . . . . .
10 V Span R to Reference Ground . . . . . . . . . . . . . . .
20 V Span R to Reference Ground . . . . . . . . . . . . . . .
12 V
12 V
12 V
24 V
Ref Out . . . . . . . . . Indefinite Short to Power Ground or +VS
1
2
24
23
22
21
20
19
18
17
16
15
14
13
(MSB) BIT 1
BIT 2
V
OUT
1
2
24
23
(MSB) BIT 1
BIT 2
V
OUT
REF
REF
REF
CONTROL
CIRCUIT
REF
CONTROL
CIRCUIT
GAIN ADJUST
GAIN ADJUST
3
BIT 3
+V
S
3
22
21
20
19
18
17
16
15
14
13
BIT 3
+V
S
4
BIT 4
COMMON
4
BIT 4
COMMON
12-BIT
RESISTOR
LADDER
NETWORK
AND
CURRENT
SWITCHES
12-BIT
5
BIT 5
SUMMING JUNCTION
20V RANGE
5
BIT 5
SCALING NETWORK
SCALING NETWORK
SCALING NETWORK
BIPOLAR OFFSET
REF INPUT
RESISTOR
LADDER
NETWORK
AND
2kꢀ
5kꢀ
5kꢀ
6
BIT 6
6
BIT 6
5kꢀ
7
BIT 7
10V RANGE
7
BIT 7
CURRENT
SWITCHES
5kꢀ
8
BIT 8
BIPOLAR OFFSET
REF INPUT
8
BIT 8
6.3kꢀ
6.3kꢀ
9
BIT 9
9
BIT 9
–
10
11
12
BIT 10
BIT 11
(LSB) BIT 12
V
10
11
12
BIT 10
BIT 11
(LSB) BIT 12
I
OUT
OUT
+
–V
–V
S
S
ADDAC80
NC/+V *
NC/+V *
L
L
*NC = CBIVERSIONS
5V – CCDVERSIONS
*NC = CBIVERSIONS
5V – CCDVERSIONS
Figure 1. Voltage Model Function Diagram
and Pin Configuration
Figure 2. Current Model Functional Diagram
and Pin Configuration
–6–
REV. B
ADI [ ADI ]
