(@ VDD = 3.3 V to 5.0 V, VGND = 0 V, TA = 25؇C, TSET = 25؇C, using typical application
ADN8830–SPECIFICATIONS configuration as shown in Figure 1, unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
TEMPERATURE STABILITY
Long-Term Stability
Using 10 kΩ thermistor with
ꢀ = –4.4% at 25°C
0.01
°C
PWM OUTPUT DRIVERS
Output Transition Time
Nonoverlapping Clock Delay
Output Resistance
Output Voltage Swing
Output Voltage Ripple
Output Current Ripple
tR, tF
CL = 3,300 pF
20
65
6
ns
ns
Ω
50
0
RO (N1, P1) IL = 50 mA
OUT A
ꢁOUT A
ꢁITEC
VLIM = 0 V
CLK = 1 MHz
VDD
V
f
0.2
0.2
%
%
fCLK = 1 MHz
LINEAR OUTPUT AMPLIFIER
Output Resistance
RO, P2
RO, N2
OUT B
IOUT = 2 mA
IOUT = 2 mA
85
178
Ω
Ω
V
Output Voltage Swing
0
VDD
5.5
POWER SUPPLY
Power Supply Voltage
Power Supply Rejection Ratio
VDD
PSRR
3.0
80
60
V
V
DD = 3.3 V to 5 V, VTEC = 0 V
92
8
dB
dB
mA
mA
μA
μA
V
–40°C ≤ TA ≤ +85°C
PWM not switching
–40°C ≤ TA ≤ +85°C
Pin 10 = 0 V
Supply Current
ISY
12
15
Shutdown Current
Soft-Start Charging Current
Undervoltage Lockout
ISD
ISS
VOLOCK
5
15
2.0
Low-to-high threshold
VCM = 1.5 V
2.7
ERROR AMPLIFIER
Input Offset Voltage
Gain
Input Voltage Range
Common-Mode Rejection Ratio
VOS
AV, IN
VCM
50
20
250
2.0
μV
V/V
V
dB
dB
0.2
58
55
CMRR
0.2 V < VCM < 2.0 V
–40°C ≤ TA ≤ +85°C
68
Open-Loop Input Impedance
Gain-Bandwidth Product
RIN
GBW
1
2
GΩ
MHz
REFERENCE VOLTAGE
Reference Voltage
VREF
IREF < 2 mA
2.37
2.47
2.57
V
OSCILLATOR
Synchronization Range
Oscillator Frequency
fCLK
fCLK
Pin 25 connected to external clock
Pin 24 = VDD; (R = 150 kΩ;
Pin 25 = GND)
200
800
1,000
1,250
kHz
kHz
1,000
LOGIC CONTROL*
Logic Low Input Threshold
Logic High Input Threshold
Logic Low Output Level
Logic High Output Threshold
0.2
0.2
V
V
V
V
3
VDD – 0.2
*Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 μA).
Specifications subject to change without notice.
D
REV.
–2–
ADI [ ADI ]
