Index
G
N
general-purpose IO pins (GPIO), 1-10, 2-9,
2-15
notation conventions, xviii
general-purpose push buttons (PB0-1), 1-10
P
package contents, 1-2
PF0-2 (IO) signals, 2-3, 2-15
PF3-15 signals, 2-3
PG0-15 signals, 2-5
PH0-2 signals, 2-6
I
installation, of this EZ-KIT Lite, 1-3
internal flash memory interface, 1-8
IO voltage, 2-2
power
connector (P9), 1-4, 2-19
LED (LED5), 2-15
measurements, 1-12
power-on-self test (POST), 1-9
programmable flag (PF)
inputs PF3-4, 1-10
J
JTAG
interface, 1-10
connector (P1), 1-4, 1-10, 2-17
jumpers
diagram of locations, 2-11
JP1 (SPI flash enable), 2-11
JP2 (voltage reference select), 2-12
JP3 (VDDEXT power), 2-12
JP4 (VDDINT power), 2-12
JP5 (VDDFLASH power), 2-12
JP6 (ADC voltage ref), 2-13
push buttons (SW7-8), 2-10
R
Reduced Instruction Set Computing (RISC), ix
reset
LEDs (LED1), 2-15
push button (SW6), 2-9
restriction, of the evaluation license, 1-7
RS-232 connector (J1), 2-17
L
LEDs
diagram of locations, 2-14
LED1 (reset), 2-15
LED2-4 (PF0-2), 1-10, 2-15
LED5 (power), 2-15
LED8 (reset), 2-15
license restrictions, x, 1-7
S
schematic, of ADSP-BF506F EZ-KIT Lite, B-1
SD connector (J3), 2-17
SPI flash memory
interface, 1-9
CS enable jumper (JP1), 2-11
SRAM memory, 1-7
See also memory map
startup, of this EZ-KIT Lite, 1-5
SW1 (UART setup) switch, 2-8
SW2 (boot mode select) switch, 2-8
M
Media Instruction Set Computing (MISC), ix
memory map, of this EZ-KIT Lite, 1-7
Micro Signal Architecture (MSA), ix
I-2
ADSP-BF506F EZ-KIT Lite Evaluation System Manual