欢迎访问ic37.com |
会员登录 免费注册
发布采购

24C04WP 参数 Datasheet PDF下载

24C04WP图片预览
型号: 24C04WP
PDF下载: 下载PDF文件 查看货源
内容描述: [用于打印机墨粉的打印控制]
分类和应用:
文件页数/大小: 14 页 / 106 K
品牌: ACUTECH [ ACUTECHNOLOGY SEMICONDUCTOR ]
 浏览型号24C04WP的Datasheet PDF文件第2页浏览型号24C04WP的Datasheet PDF文件第3页浏览型号24C04WP的Datasheet PDF文件第4页浏览型号24C04WP的Datasheet PDF文件第5页浏览型号24C04WP的Datasheet PDF文件第6页浏览型号24C04WP的Datasheet PDF文件第7页浏览型号24C04WP的Datasheet PDF文件第8页浏览型号24C04WP的Datasheet PDF文件第9页  
NM24C04/05 – 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM
February 2000
NM24C04/05 – 4K-Bit Standard 2-Wire Bus
Interface Serial EEPROM
General Description
The NM24C04/05 devices are 4096 bits of CMOS non-volatile
electrically erasable memory. These devices conform to all speci-
fications in the Standard IIC 2-wire protocol and are designed to
minimize device pin count, and simplify PC board layout require-
ments.
The upper half (upper 2Kbit) of the memory of the NM24C05 can be
write protected by connecting the WP pin to V
CC
. This section of
memory then becomes unalterable unless WP is switched to V
SS
.
This communications protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
The Standard IIC protocol allows for a maximum of 16K of
EEPROM memory which is supported by the Fairchild family in
2K, 4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of
EEPROMs. In order to implement higher EEPROM memory
densities on the IIC bus, the Extended IIC protocol must be used.
(Refer to the NM24C32 or NM24C65 datasheets for more infor-
mation.)
Fairchild EEPROMs are designed and tested for applications requir-
ing high endurance, high reliability and low power consumption.
Features
I
Extended operating voltage 2.7V – 5.5V
I
400 KHz clock frequency (F) at 2.7V - 5.5V
I
200µA active current typical
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
I
IIC compatible interface
– Provides bi-directional data transfer protocol
I
Schmitt trigger inputs
I
Sixteen byte page write mode
– Minimizes total write time per byte
I
Self timed write cycle
Typical write cycle time of 6ms
I
Hardware Write Protect for upper half (NM24C05 only)
I
Endurance: 1,000,000 data changes
I
Data retention greater than 40 years
I
Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP
I
Available in three temperature ranges
- Commercial: 0° to +70°C
- Extended (E): -40° to +85C
- Automotive (V): -40° to +125°C
Block Diagram
VCC
VSS
WP
H.V. GENERATION
TIMING &CONTROL
START
STOP
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER &
COMPARATOR
E2PROM
ARRAY
SDA
SCL
XDEC
A2
A1
WORD
ADDRESS
COUNTER
R/W
YDEC
CK
DIN
DATA REGISTER
DOUT
DS500070-1
© 1998 Fairchild Semiconductor Corporation
NM24C04/05 Rev. G
1
www.fairchildsemi.com