PAC5253
Power Application Controller
15. CLOCK CONTROL SYSTEM
15.1. Features
Ring oscillator with 7.5MHz, 9.6MHz, 13.8MHz, and 25.7MHz settings
High accuracy 2% trimmed 4MHz RC oscillator
Crystal oscillator driver supporting 2MHz to 10MHz crystals
External clock input up to 40MHz
PLL with 1MHz to 25 MHz input, and 3.5MHz to 100MHz output
/1 to /8 clock divider for HCLK
/1 to /128 clock divider for ACLK
15.2. Block Diagram
Figure 15-1 Clock Control System
CLOCK CONTROL SYSTEM
FRCLK
DIV
DIV
DIV
DIV
DIV
RTC
WDT
WIC
CLOCK
GATING
ADC
SYSTICK
CORTEX M0
SRAM
CLOCK SOURCES
PLL
CLOCK TREE
RING
OSCILLATOR
FLASH
UART
FCLK
HCLK
2% RC
OSCILLATOR
DIV
DIV
DIV
DIV
DIV
CLOCK
GATING
DIV
DIV
PLL
EXTCLK
XIN
I2C
CRYSTAL
DRIVER
ACLK
XOUT
SOC BUS
SPI
ADC EMUX
TIMERS A, B, C & D
DIV TIMER
CLOCK
GATING
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Rev 1.24‒March 3, 2018