PAC5253
Power Application Controller
Table 7. I/O Ports Pin Description
PIN NAME
PIN NUMBER
FUNCTION
PC2
TYPE
DESCRIPTION
I/O
I/O port C2.
PC2/AD2
3
AD2
Analog ADC input 2.
PD0
I/O
I/O
I/O
I
I/O port D0.
PD0/SWDIO
36
35
SWDIO
PD1
Serial wire debug I/O.
I/O port D1.
PD1/SWDCL/EXTCLK
SWDCL
EXTCLK
PD2
Serial wire debug clock.
External clock.
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O port D2.
PWMA3
PWMA4
PWMB0
PE0
Timer A PWM/capture 3.
Timer A PWM/capture 4.
Timer B PWM/capture 0.
I/O port E0.
PD2/PWMA3/PWMA4/PWMB0
34
PE0/SPICLK
37
38
SPICLK
PE1
SPI clock.
I/O port E1.
PE1/SPIMOSI/UARTTX
SPIMOSI
UARTTX
PE2
SPI master out slave in (MOSI).
UART transmit output.
I/O port E2.
I/O
I/O
I
PE2/SPIMISO/UARTRX
PE3/SPICS0/nRESET1
PE4/SPICS1/I2CSCL
PE5/SPICS2/I2CSDA
39
40
41
SPIMISO
UARTRX
PE3
SPI master in slave out (MISO).
UART receive input.
I/O port E3.
I/O
O
SPICS0
nRESET1
PE4
SPI chip select 0.
Reset input 1 (active low).
I/O port E4.
I
I/O
O
SPICS1
I2CSCL
PE5
SPI chip select 1.
I2C clock.
I/O
I/O
O
I/O port E5.
SPICS2
I2CSDA
SPI chip select 2.
I2C data.
42
I/O
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Rev 1.24‒March 3, 2018
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
