PAC5253
Power Application Controller
7. ARCHITECTURAL BLOCK DIAGRAM
Figure 7-1. Architectural Block Diagram
PAC5253
MULTI-MODE POWER
MANAGER
Power Application Controller
VHM
DRM
VP
CSM
VSS
MULTI-
MODE
SWITCHING
SUPPLY
SWDIO, SWDCL
DEBUG
32kB/16kB
FLASH
REGO
VSYS
VCCIO
VCC33
VCC18
LINEAR
REGU-
LATORS
(4)
ARM
CORTEX-M0
8kB/4kB
CORE
SRAM
APPLICATION SPECIFIC
POWER DRIVERS
PWM ENGINE
CLOCK
CONTROL
TIMERS (4)
DXBx
DXHx
DXSx
HSGD (3)
LSGD (4)
PWMAx, PWMBx
PWM /
CC (14)
RTC
DRLx
DEAD TIME
(7)
PCx, PDx, PEx
GPIO (10)
CONFIGURABLE
ANALOG FRONT END
BRIDGE
SPICSx, SPIMISO,
SPIMOSI, SPICLK
PGA/
CMP (4)
SPI
AMPx/CMPx/PHCx
WATCHDOG
DAC (2)
I2CSDA, I2CSCL
UARTRX, UARTTX
nRESET1
I2C
DATA ACQUISITION &
SEQUENCER
DAxP/PCMPx
DAxN
DIFF-PGA/
PCMP (3)
UART
10-BIT
ADC
ADx
AUTO
SAMPLING
AIOx
BUF6
PBTN
AIO
CONTROL
(10)
SYSTEM
CONTROL
- 12 -
Rev 1.24‒March 3, 2018
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
