PAC5250
Power Application Controller
Figure 12-3. High-Side Switching Transients and Optional Circuitry
V
≤ 625V
DXBx
DXBx
V
P
V
IN
DXHx
DXSx
dV/dt
PAC5250
V
V
DXBx
dV/dt
DRLx
DXSx
V
≥ -10V
DXSx
(b) Optional Transient Protection and Slew Rate Control
(a) High-Side Switching Transients
12.3.4. Open-Drain Drivers
The OMx pin is a 23V open-drain driver output controlled by a register bit. OMx is capable of driving 40mA. The OMx pin
is switched to VSSP with 17Ω impedance in the on state when the corresponding bit is '1', and is in the high-impedance off
state when the corresponding bit is '0'.
12.3.5. Power Drivers Control
All power drivers are initially disabled from power-on-reset. To enable the power drivers, the microprocessor must first set
the driver enable bit to '1'. The gate drivers controlled by the microcontroller ports and PWM signals according to Table 22,
with configurable delays as shown in Table 22. The OMx open-drain drivers are controlled by their corresponding register
bits. Refer to the PAC application notes and user guide for additional information on power drivers control programming.
Table 22. Microcontroller Port and PWM to Power Driver Mapping
PWMA3/
PWMA4/
PWMB0
PWMA5/
PWMA7/
PWMC1
PART
NUMBER
PWMA5/
PWMC0
PWMA6/
PWMD0
PWMA4/
PWMB0
PWMA6/
PWMD0
PWMA0
PWMA1
PWMA2
PAC5250
DRL0
DRL1
DRL2
DRL3
DRL4
DRL5
DXH0
DXH1
DXH2
Table 23. Power Driver Propagation Delay
DRLx
DXHx
RISING
FALLING
140ns
RISING
200ns
FALLING
130ns
240ns
12.3.6. Gate Driver Fault Protection
The ASPD incorporates a configurable fault protection mechanism using two protection event signals from the
Configurable Analog Front End (CAFE), designated as protection event 1 (PR1) and protection event 2 (PR2) signals. The
DRL0/DRL1/DRL2 drivers are designated as low-side group 1, and the DRL3/DRL4/DRL5 gate drivers are designed as
low-side group 2. The DXH0/DXH1/DXH2 ultra-high-voltage gate drivers are designated as high-side group 1. The PR1
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Rev 1.14‒June 15, 2017
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
