PAC5250
Power Application Controller
Table 7. I/O Ports Pin Description
PIN NAME
PIN NUMBER
FUNCTION
PC2
TYPE
DESCRIPTION
I/O
I/O port C2.
PC2/AD2
4
AD2
Analog ADC input 2.
I/O I/O port C3.
Analog ADC input 3.
PC3
PC3/AD3
3
AD3
PD0
I/O
I/O
I/O
I
I/O port D0.
PD0/SWDIO
49
SWDIO
PD1
Serial wire debug I/O.
I/O port D1.
PD1/SWDCL/EXTCLK
48
47
SWDCL
EXTCLK
PD2
Serial wire debug clock.
External clock.
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O port D2.
PWMA3
PWMA4
PWMB0
PD3
Timer A PWM/capture 3.
Timer A PWM/capture 4.
Timer B PWM/capture 0.
I/O port D3.
PD2/PWMA3/PWMA4/PWMB0
PWMA5
PWMA7
PWMB1
PD4
Timer A PWM/capture 5.
Timer A PWM/capture 7.
Timer B PWM/capture 1.
I/O port D4.
PD3/PWMA5/PWMA7/PWMB1
46
PD4/PWMD1
45
44
PWMD1
PD5
Timer D PWM/capture 1.
I/O port D5.
PD5/PWMA5/PWMC1
PWMA5
PWMC1
PD6
Timer A PWM/capture 5.
Timer C PWM/capture 1.
I/O port D6.
PD6/PWMA7/PWMB1
PE0/SPICLK
43
50
51
PWMA7
PWMB1
PE0
Timer A PWM/capture 7.
Timer B PWM/capture 1.
I/O port E0.
SPICLK
PE1
SPI clock.
I/O port E1.
PE1/SPIMOSI/UARTTX
SPIMOSI
UARTTX
PE2
SPI master out slave in (MOSI).
UART transmit output.
I/O port E2.
I/O
I/O
I
PE2/SPIMISO/UARTRX
52
SPIMISO
UARTRX
SPI master in slave out (MISO).
UART receive input.
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Rev 1.14‒June 15, 2017