PAC5250
Power Application Controller
7. ARCHITECTURAL BLOCK DIAGRAM
Figure 7-1. Architectural Block Diagram
PAC5250
MULTI-MODE POWER
MANAGER
Power Application Controller
VHM
MULTI-
MODE
SWITCHING
SUPPLY
SWDIO, SWDCL
DRM
VP
CSM
VSSP, VSS, VSSA
DEBUG
32kB/16kB
FLASH
REGO
VSYS
VCCIO
VCC33
VCC18
LINEAR
REGU-
LATORS
(4)
ARM
CORTEX-M0
8kB/4kB
CORE
SRAM
APPLICATION SPECIFIC
POWER DRIVERS
OM0
OM2
OD (2)
PWM ENGINE
CLOCK
XIN, XOUT
CONTROL
TIMERS (4)
DXBx
DXHx
HSGD (3)
LSGD (6)
PWMAx, PWMBx,
PWMCx, PWMDx
DXSx
PWM /
CC (14)
ENHS2
RTC
GPIO (15)
SPI
DRLx
DEAD TIME
(7)
PCx, PDx, PEx
CONFIGURABLE
ANALOG FRONT END
BRIDGE
SPICSx, SPIMISO,
SPIMOSI, SPICLK
PGA/
CMP (4)
AMPx/CMPx/PHCx
WATCHDOG
DAC (2)
I2CSDA, I2CSCL
UARTRX, UARTTX
nRESET1
I2C
DATA ACQUISITION &
SEQUENCER
DAxP/PCMPx
DAxN
DIFF-PGA/
PCMP (3)
UART
10-BIT
ADC
ADx
AUTO
SAMPLING
AIOx
BUF6
PBTN
AIO
CONTROL
(10)
SYSTEM
CONTROL
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Rev 1.14‒June 15, 2017
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
