PAC5225
Power Application Controller
Figure 19-2. SOC Bus Watchdog and Wake-Up Timer
SOC BUS WATCHDOG AND WAKE-UP TIMER
SOC
SOC BUS
WATCHDOG
WAKE-UP
TIMER
SOC BUS
Figure 19-3. Real-Time Clock and Watchdog Timer
REAL-TIME CLOCK AND WATCHDOG TIMER
RTC
24-BIT
WDT
24-BIT
19.2. Functional Description
The device includes 9 timers: timer A, timer B, timer C, timer D, watchdog timer 1 (WDT), watchdog timer 2, wake-up
timer, real-time clock (RTC), and SysTick timer. The device supports up to 14 different PWM signals and has up to 7 dead-
time controllers. Timers A, B, C and D can be concatenated to synchronize to a single clock and start/stop signal for
applications that require a synchronized timer period between timers.
19.2.1. Timer A
Timer A is a general purpose 16-bit timer with 8 PWM/capture and compare units. It has 4 pairs of PWM signals going into
4 dead-time controllers. Timer A can be concatenated with timers B, C, and D to synchronize the PWM/capture and
compare units. It can use either ACLK or HCLK as clock input with an additional clock divider from /1 to /128.
19.2.2. Timer B
Timer B is a general purpose 16-bit timer with 2 PWM/capture and compare units. It has one pair of PWM signals going
into one dead-time controller, as well as 2 additional compare units that can be used for additional system time bases for
interrupts. Timer B can be concatenated with timers A, C, and D to synchronize the PWM/capture and compare units. It can
use either ACLK or HCLK as clock input with an additional clock divider from /1 to /128.
19.2.3. Timer C
Timer C is a general purpose 16-bit timer with 2 PWM/capture and compare units. It has one pair of PWM signals going
into one dead-time controller. Timer C can be concatenated with timers A, B, and D to synchronize the PWM/capture and
compare units. It can use either ACLK or HCLK as clock input with an additional clock divider from /1 to /128.
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Rev 2.0‒September 22, 2017
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
