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PAC5225QM 参数 Datasheet PDF下载

PAC5225QM图片预览
型号: PAC5225QM
PDF下载: 下载PDF文件 查看货源
内容描述: [Power Application Controller]
分类和应用:
文件页数/大小: 71 页 / 931 K
品牌: ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
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PAC5225  
Power Application Controller  
Figure 10-4. Flyback Mode  
VHM  
V
(120V/230V)  
AC  
PAC5225  
VP  
DRM  
CSM  
V
(15V default)  
P
The MMSS detects and selects between high-side and low-side mode during start up based on the placement of the current  
sense resistor and the CSM pin voltage. It employs a safe start up mode with a 9.5kHz switching frequency until VP exceeds  
4.3V under-voltage-lockout threshold, then transitions to the 45kHz default switching frequency for at least 6ms to bring VP  
close to the target voltage, before enabling the linear regulators. Any extra load should only be applied after the supplies are  
available and the microprocessor has initialized. The switching frequency can be reconfigured by the microprocessor to be  
181kHz to 500kHz in the high switching frequency mode for battery-based applications, and to be 45kHz to 125kHz in the  
low switching frequency mode for AC applications. Upon initialization, the microcontroller must reconfigure the MMSS to  
the desired settings for VP regulation voltage, switching mode, switching frequency, and VHM clamp. Refer to the PAC  
application notes and user guide for MMSS controller design and programming.  
If a stable external 5V to 18V power source is available, it can power the VP main supply and all the linear regulators  
directly without requiring the MMSS controller to operate. In such applications, VHM can be connected directly to VP and  
the microcontroller should disable the MMSS upon initialization to reduce power loss.  
10.3.2. Linear Regulators  
The MMPM includes up to four linear regulators. The system supply regulator is a medium voltage regulator that takes the  
VP supply and sources up to 200mA at REGO until VSYS, externally coupled to REGO, reaches 5V. This allows a properly  
rated external resistor to be connected from REGO to VSYS to close the current loop and offload power dissipation between  
VP and VSYS. Once VSYS is above 4V, the three additional 40mA linear regulators for VCCIO, VCC33, and VCC18 supplies  
sequentially power up. Figure 10-5 shows typical circuit connections for the linear regulators. For 5V I/O systems, short the  
VCCIO pin to VSYS to bypass the VCCIO regulator. For 3.3V I/O systems, the VCCIO regulator generates 3.3V. The VCC33 and  
VCC18 regulators generate 3.3V and 1.8V, respectively. When VSYS, VCCIO, VCC33, and VCC18 are all above their respective  
power good thresholds, and the configurable power on reset duration has expired, the microcontroller is initialized.  
- 22 -  
Rev 2.0‒September 22, 2017  
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