PAC5225
Power Application Controller
Table 8. I/O Ports Pin Description (Continued)
PIN NAME
PIN NUMBER
FUNCTION
PA7
TYPE
DESCRIPTION
Digital I/O port A7.
PWMA5
PWMA7
PWMC1
CLKOUT
PD0
Digital Timer A PWM/Capture 5.
Digital Timer A PWM/Capture 7.
Digital Timer C PWM/Capture 1.
Digital Low-speed clock output
PA7/PWMA5/PWMA7/PAMC1/
CLKOUT
33
I/O
I/O
I/O
I
I/O port D0.
PD0/SWDIO
39
38
SWDIO
PD1
Serial wire debug I/O.
I/O port D1.
PD1/SWDCL/EXTCLK
SWDCL
EXTCLK
PD2
Serial wire debug clock.
External clock.
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O port D2.
PWMA3
PWMA4
PWMB0
PD3
Timer A PWM/capture 3.
Timer A PWM/capture 4.
Timer B PWM/capture 0.
I/O port D3.
PD2/PWMA3/PWMA4/PWMB0
37
PWMA5
PWMA7
PWMB1
PD5
Timer A PWM/capture 5.
Timer A PWM/capture 7.
Timer B PWM/capture 1.
I/O port D5.
PD3/PWMA5/PWMA7/PWMB1
PD5/PWMA5/PWMC1
36
35
PWMA5
PWMC1
PD7
Timer A PWM/capture 5.
Timer C PWM/capture 1.
I/O port D7.
PD7/PWMA6/PWMD0
PE0/SPICLK
34
40
41
PWMA6
PWMD0
PE0
Timer A PWM/capture 6.
Timer D PWM/capture 0.
I/O port E0.
SPICLK
PE1
SPI clock.
I/O port E1.
PE1/SPIMOSI/UARTTX
SPIMOSI
UARTTX
PE2
SPI master out slave in (MOSI).
UART transmit output.
I/O port E2.
I/O
I/O
I
PE2/SPIMISO/UARTRX
42
SPIMISO
UARTRX
SPI master in slave out (MISO).
UART receive input.
- 17 -
Rev 2.0‒September 22, 2017
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
