PAC5223
Power Application Controller
6. ARCHITECTURAL BLOCK DIAGRAM
Figure 6-1. Architectural Block Diagram
PAC5223
MULTI-MODE POWER
MANAGER
Power Application Controller
VHM
MULTI-
MODE
SWITCHING
SUPPLY
SWDIO, SWDCL
DRM
VP
CSM
VSSP, VSS, VSSA
DEBUG
32kB/16kB
FLASH
REGO
VSYS
VCCIO
VCC33
VCC18
LINEAR
REGU-
LATORS
(4)
ARM
CORTEX-M0
8kB/4kB
CORE
SRAM
APPLICATION SPECIFIC
POWER DRIVERS
DRBx
DRHx
DRSx
PWM ENGINE
HSGD (3)
LSGD (3)
CLOCK
CONTROL
TIMERS (4)
PWMAx, PWMBx,
PWMCx, PWMDx
PWM /
CC (14)
DRLx
RTC
GPIO (15)
SPI
DEAD TIME
(7)
PCx, PDx, PEx
CONFIGURABLE
ANALOG FRONT END
BRIDGE
SPICSx, SPIMISO,
SPIMOSI, SPICLK
PGA/
CMP (4)
AMPx/CMPx/PHCx
WATCHDOG
DAC (2)
I2CSDA, I2CSCL
UARTRX, UARTTX
nRESET1
I2C
DATA ACQUISITION &
SEQUENCER
DAxP/PCMPx
DAxN
DIFF-PGA/
PCMP (3)
UART
10-BIT
ADC
ADx
AUTO
SAMPLING
AIOx
BUF6
PBTN
AIO
CONTROL
(10)
SYSTEM
CONTROL
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Rev 1.17‒September 20, 2017
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
