PAC5220
Power Application Controller
Table 9-5. I/O Ports Pin Description (Continued)
PIN NAME
PIN NUMBER
FUNCTION
PD0
TYPE
I/O
I/O
I/O
I
DESCRIPTION
I/O port D0.
PD0/SWDIO
46
SWDIO
PD1
Serial wire debug I/O.
I/O port D1.
PD1/SWDCL/EXTCLK
45
44
SWDCL
EXTCLK
PD2
Serial wire debug clock.
External clock.
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I/O port D2.
PWMA3
PWMA4
PWMB0
PD3
Timer A PWM/capture 3.
Timer A PWM/capture 4.
Timer B PWM/capture 0.
I/O port D3.
PD2/PWMA3/PWMA4/PWMB0
PWMA5
PWMA7
PWMB1
PD4
Timer A PWM/capture 5.
Timer A PWM/capture 7.
Timer B PWM/capture 1.
I/O port D4.
PD3/PWMA5/PWMA7/PWMB1
43
PD4/PWMD1
42
41
PWMD1
PD5
Timer D PWM/capture 1.
I/O port D5.
PD5/PWMA5/PWMC1
PWMA5
PWMC1
PD6
Timer A PWM/capture 5.
Timer C PWM/capture 1.
I/O port D6.
PD6/PWMA7/PWMB1
40
PWMA7
PWMB1
PD7
Timer A PWM/capture 7.
Timer B PWM/capture 1.
I/O port D7.
PD7/PWMA6/PWMD0
PE0/SPICLK
39
47
48
PWMA6
PWMD0
PE0
Timer A PWM/capture 6.
Timer D PWM/capture 0.
I/O port E0.
SPICLK
PE1
SPI clock.
I/O port E1.
PE1/SPIMOSI/UARTTX
SPIMOSI
UARTTX
PE2
SPI master out slave in (MOSI).
UART transmit output.
I/O port E2.
I/O
I/O
I
PE2/SPIMISO/UARTRX
49
SPIMISO
UARTRX
SPI master in slave out (MISO).
UART receive input.
- 17 -
Rev 1.11‒June 15, 2017
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
