PAC5210
Power Application Controller
the PWM/capture and compare units. It can use either ACLK or HCLK as clock input with an additional clock
divider from /1 to /128.
19.2.4. Timer D
Timer D is a general purpose 16-bit timer with 2 PWM/capture and compare units. It has one pair of PWM
signals going into one dead-time controller. Timer D can be concatenated with timers A, B, and C to synchronize
the PWM/capture and compare units. It can use either ACLK or HCLK as clock input with an additional clock
divider from /1 to /128.
19.2.5. Watchdog Timer
The 24-bit watchdog timer (WDT) can be used for long time period measurements or periodic wake up from
sleep mode. The watchdog timer can be used as a system watchdog, or as an interval timer, or both. The
watchdog timer can use either FRCLK or FCLK as clock input with an additional clock divider from /2 to /65536.
19.2.6. SOC Bus Watchdog Timer
The watchdog timer 2 is used to monitor internal SOC Bus communication. It will trigger device reset if there is
no SOC Bus communication to the AFE for 4s or 8s.
19.2.7. Wake-Up Timer
The wake-up timer can be used for very low power hibernate and sleep modes to wake up the micro controller
periodically. It can be configured to be 125ms, 250ms, 500ms, 1s, 2s, 4, or 8s.
19.2.8. Real-Time Clock
The 24-bit real-time clock (RTC) can be used for time measurements when an accurate clock source is used.
This timer can also be used for periodic wake up from sleep mode. The RTC uses FRCLK as clock input with an
additional clock divider from /2 to /65536.
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Rev 1.11‒May 3, 2017
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
