PAC5210
Power Application Controller
LIST OF FIGURES
Figure 1-1. Power Application Controller................................................................................................................7
Figure 2-1. Simplified Application Diagram............................................................................................................8
Figure 7-1. Architectural Block Diagram...............................................................................................................12
Figure 8-1. PAC5210QS Pin Configuration (TQFN88-56 Package).....................................................................13
Figure 9-1. Power Supply Bypass Capacitor Routing..........................................................................................20
Figure 10-1. Multi-Mode Power Manager.............................................................................................................21
Figure 10-2. Buck Mode.......................................................................................................................................22
Figure 10-3. Ultra-High-Voltage Buck Mode.........................................................................................................22
Figure 10-4. AC/DC Flyback Mode.......................................................................................................................23
Figure 10-5. Linear Regulators.............................................................................................................................24
Figure 10-6. Power Up Sequence........................................................................................................................24
Figure 11-1. Configurable Analog Front End........................................................................................................30
Figure 12-1. Application Specific Power Drivers...................................................................................................39
Figure 13-1. ADC with Auto-Sampling Sequencer................................................................................................43
Figure 14-1. Memory System...............................................................................................................................46
Figure 15-1. Clock Control System......................................................................................................................49
Figure 16-1. ARM Cortex-M0 Microcontroller Core..............................................................................................52
Figure 17-1. I/O controller....................................................................................................................................55
Figure 18-1. Serial Interface.................................................................................................................................57
Figure 18-2. I2C Timing Diagram..........................................................................................................................61
Figure 18-3. SPI Timing Diagram.........................................................................................................................62
Figure 19-1. Timers A, B, C, and D......................................................................................................................63
Figure 19-2. SOC Bus Watchdog and Wake-Up Timer........................................................................................64
Figure 19-3. Real-Time Clock and Watchdog Timer.............................................................................................64
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Rev 1.11‒May 3, 2017
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
