PAC5210
Power Application Controller
SYMBOL
ADC
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
fADCLK
ADC conversion clock input
ADC conversion time
ADC resolution
16
1
MHz
μs
tADCONV
fADCLK = 16MHz
10
bits
ADC effective resolution
ADC differential non-linearity (DNL)
ADC integral non-linearity (INL)
ADC offset error
9.2
bits
±0.5
±1
LSB
LSB
%FS
%FS
0.6
ADC gain error
0.12
Reference Voltage
VREFADC
ADC reference voltage input
2.5
V
Sample and Hold
tADCSH
CADCIC
Input Voltage Range
ADC sample and hold time
fADCLK = 16MHz
188
1.3
ns
ADC input capacitance
pF
VADCIN
ADC input voltage range
ADC multiplexer input
0
VREFADC
V
EMUX Clock Speed
fEMUXCLK
EMUX engine clock input
50
MHz
PLL Clock Speed
fOUTPLL
PLL output frequency
TA = -40°C to 85°C
TA = 85°C to 105°C
3.5
3.5
100
80
MHz
MHz
- 45 -
Rev 1.11‒May 3, 2017
ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
