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ACT8938QJ133-T 参数 Datasheet PDF下载

ACT8938QJ133-T图片预览
型号: ACT8938QJ133-T
PDF下载: 下载PDF文件 查看货源
内容描述: [Advanced PMU for Marvell Aspen]
分类和应用:
文件页数/大小: 46 页 / 1008 K
品牌: ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
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®
ACT8938  
Rev 3, 23-Dec-11  
REGISTER AND BIT DESCRIPTIONS CONT’D  
OUTPUT ADDRESS BIT  
NAME  
ACCESS  
DESCRIPTION  
Regulator Power-OK Status. Value is 1 when output voltage  
exceeds the power-OK threshold, value is 0 otherwise.  
REG6  
REG7  
REG7  
0x61  
0x64  
0x64  
[0]  
OK  
-
R
R
[7:6]  
[5:0]  
Reserved.  
Output Voltage Selection. See the Output Voltage  
Programming section for more information.  
VSET  
R/W  
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear  
bit to 0 to disable the regulator.  
REG7  
REG7  
0x65  
0x65  
[7]  
[6]  
ON  
R/W  
R/W  
Output Discharge Control. When activated, LDO output is  
discharged to GA through 1.5kresistor when in shutdown.  
Set bit to 1 to enable output voltage discharge in shutdown,  
clear bit to 0 to disable this function.  
DIS  
LDO Low-IQ Mode Control. Set bit to 1 for low-power  
operating mode, clear bit to 0 for normal mode.  
REG7  
REG7  
REG7  
0x65  
0x65  
0x65  
[5]  
[4:2]  
[1]  
LOWIQ  
DELAY  
R/W  
R/W  
R/W  
R
Regulator Turn-On Delay Control. See the REG4, REG5,  
REG6, REG7 Turn-on Delay section for more information.  
Regulator Fault Mask Control. Set bit to 1 enable fault-  
interrupts, clear bit to 0 to disable fault-interrupts.  
nFLTMSK  
Regulator Power-OK Status. Value is 1 when output voltage  
exceeds the power-OK threshold, value is 0 otherwise.  
REG7  
APCH  
APCH  
APCH  
APCH  
0x65  
0x70  
0x71  
0x71  
0x71  
[0]  
[7:0]  
[7]  
OK  
-
R/W Reserved.  
Charge Suspend Control Input. Set bit to 1 to suspend  
charging, clear bit to 0 to allow charging to resume.  
SUSCHG  
-
R/W  
[6]  
R/W Reserved.  
Total Charge Time-out Selection. See the Charge Safety  
Timers section for more information.  
[5:4]  
TOTTIMO  
R/W  
R/W  
R/W  
Precondition Charge Time-out Selection. See the Charge  
Safety Timers section for more information.  
APCH  
APCH  
0x71  
0x71  
[3:2]  
[1:0]  
PRETIMO  
OVPSET  
Input Over-Voltage Protection Threshold Selection. See the  
Input Over-Voltage Protection section for more information.  
Charge Time-out Interrupt Status. Set this bit with  
TIMRPRE[ ] and/or TIMRTOT[ ] to 1 to generate an interrupt  
APCH  
APCH  
APCH  
0x78  
0x78  
0x78  
[7]  
[6]  
[5]  
TIMRSTAT1  
TEMPSTAT1  
INSTAT  
R/W when charge safety timers expire, read this bit to get charge  
time-out interrupt status. See the Charge Safety Timers  
section for more information.  
Battery Temperature Interrupt Status. Set this bit with  
TEMPIN[ ] and/or TEMPOUT[ ] to 1 to generate an interrupt  
R/W when a battery temperature event occurs, read this bit to get  
the battery temperature interrupt status. See the Battery  
Temperature Monitoring section for more information.  
Input Voltage Interrupt Status. Set this bit with INCON[ ] and/or  
INDIS[ ] to generate an interrupt when UVLO or OVP condition  
R/W occurs, read this bit to get the input voltage interrupt status.  
See the Charge Current Programming section for more  
information.  
Charge State Interrupt Status. Set this bit with  
CHGEOCIN[ ] and/or CHGEOCOUT[ ] to 1 to generate an  
R/W interrupt when the state machine gets in or out of EOC state,  
read this bit to get the charger state interrupt status. See the  
State Machine Interrupts section for more information.  
APCH  
APCH  
0x78  
0x78  
[4]  
[3]  
CHGSTAT1  
TIMRDAT1  
Charge Timer Status. Value is 1 when precondition time-out or  
R
total charge time-out occurs. Value is 0 in other case.  
Innovative PowerTM  
www.active-semi.com  
- 13 -  
Active-Semi ProprietaryFor Authorized Recipients and Customers  
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.  
I2CTM is a trademark of NXP.  
Copyright © 2011 Active-Semi, Inc.