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ACT8937AQJ1PQ-T 参数 Datasheet PDF下载

ACT8937AQJ1PQ-T图片预览
型号: ACT8937AQJ1PQ-T
PDF下载: 下载PDF文件 查看货源
内容描述: 先进的PMU三星S5PC100 , S5PC110和S5PV210处理器 [Advanced PMU for Samsung S5PC100, S5PC110 and S5PV210 Processors]
分类和应用: PC
文件页数/大小: 45 页 / 845 K
品牌: ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
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ACT8937A  
Rev 1, 22-Oct-12  
REGISTER AND BIT DESCRIPTIONS CONT’D  
OUTPUT ADDRESS BIT  
NAME  
ACCESS  
DESCRIPTION  
Secondary Output Voltage Selection. Valid when VSEL is  
driven high. See the Output Voltage Programming section for  
more information.  
REG2  
REG2  
0x31  
0x32  
[5:0]  
[7]  
VSET2  
R/W  
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear  
bit to 0 to disable the regulator.  
ON  
R/W  
R/W  
Regulator Phase Control. Set bit to 1 for the regulator to  
operate 180° out of phase with the oscillator, clear bit to 0 for  
the regulator to operate in phase with the oscillator.  
REG2  
REG2  
0x32  
0x32  
[6]  
[5]  
PHASE  
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM  
under all load conditions, clear bit to 0 to transit to power-  
savings mode under light-load conditions.  
MODE  
R/W  
Regulator Turn-On Delay Control. See the REG1, REG2,  
REG3 Turn-on Delay section for more information.  
REG2  
REG2  
0x32  
0x32  
[4:2]  
[1]  
DELAY  
R/W  
R/W  
Regulator Fault Mask Control. Set bit to 1 enable fault-  
interrupts, clear bit to 0 to disable fault-interrupts.  
nFLTMSK  
Regulator Power-OK Status. Value is 1 when output voltage  
exceeds the power-OK threshold, value is 0 otherwise.  
REG2  
REG3  
0x32  
0x40  
[0]  
OK  
-
R
R
[7:6]  
Reserved.  
Primary Output Voltage Selection. Valid when VSEL is driven  
low. See the Output Voltage Programming section for more  
information.  
REG3  
REG3  
REG3  
0x40  
0x41  
0x41  
[5:0]  
[7:6]  
[5:0]  
VSET1  
-
R/W  
R
Reserved.  
Secondary Output Voltage Selection. Valid when VSEL is  
driven high. See the Output Voltage Programming section for  
more information.  
VSET2  
R/W  
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear  
bit to 0 to disable the regulator.  
REG3  
REG3  
0x42  
0x42  
[7]  
[6]  
ON  
-
R/W  
R/W  
Reserved.  
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM  
under all load conditions, clear bit to 0 to transit to power-  
savings mode under light-load conditions.  
REG3  
0x42  
[5]  
MODE  
R/W  
Regulator Turn-On Delay Control. See the REG1, REG2,  
REG3 Turn-on Delay section for more information.  
REG3  
REG3  
0x42  
0x42  
[4:2]  
[1]  
DELAY  
R/W  
R/W  
Regulator Fault Mask Control. Set bit to 1 enable fault-  
interrupts, clear bit to 0 to disable fault-interrupts.  
nFLTMSK  
Regulator Power-OK Status. Value is 1 when output voltage  
exceeds the power-OK threshold, value is 0 otherwise.  
REG3  
REG4  
REG4  
0x42  
0x50  
0x50  
[0]  
OK  
-
R
R
[7:6]  
[5:0]  
Reserved.  
Output Voltage Selection. See the Output Voltage  
Programming section for more information.  
VSET  
R/W  
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear  
bit to 0 to disable the regulator.  
REG4  
REG4  
0x51  
0x51  
[7]  
[6]  
ON  
R/W  
R/W  
Output Discharge Control. When activated, LDO output is  
discharged to GA through 1.5kresistor when in shutdown.  
Set bit to 1 to enable output voltage discharge in shutdown,  
clear bit to 0 to disable this function.  
DIS  
LDO Low-IQ Mode Control. Set bit to 1 for low-power  
operating mode, clear bit to 0 for normal mode.  
REG4  
REG4  
REG4  
0x51  
0x51  
0x51  
[5]  
[4:2]  
[1]  
LOWIQ  
DELAY  
R/W  
R/W  
R/W  
Regulator Turn-On Delay Control. See the REG4, REG5,  
REG6, REG7 Turn-on Delay section for more information.  
Regulator Fault Mask Control. Set bit to 1 enable fault-  
interrupts, clear bit to 0 to disable fault-interrupts.  
nFLTMSK  
Innovative PowerTM  
www.active-semi.com  
- 11 -  
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.  
I2CTM is a trademark of NXP.  
Copyright © 2012 Active-Semi, Inc.