ACT8935
Rev 4, 17-Sep-13
REGISTER AND BIT DESCRIPTIONS
Table 1:
Global Register Map
OUTPUT ADDRESS BIT
NAME
ACCESS
DESCRIPTION
Reset Timer Setting. Defines the reset time-out threshold. Reset
time-out is 65ms when value is 1, reset time-out is 260ms when
value is 0. See nRSTO Output section for more information.
SYS
SYS
0x00
0x00
[7]
TRST
R/W
SYSLEV Mode Select. Defines the response to the SYSLEV
voltage detector, 1: Generate an interrupt when VVSYS falls
below the programmed SYSLEV threshold, 0: automatic
shutdown when VVSYS falls below the programmed SYSLEV
threshold.
[6]
nSYSMODE
R/W
System Voltage Level Interrupt Mask. SYSLEV interrupt is
masked by default, set to 1 to unmask this interrupt. See the
Programmable System Voltage Monitor section for more
information
SYS
SYS
0x00
0x00
[5] nSYSLEVMSK R/W
System Voltage Status. Value is 1 when VVSYS is lower than the
SYSLEV voltage threshold, value is 0 when VVSYS is higher than
the system voltage detection threshold.
[4]
nSYSSTAT
R
System Voltage Detect Threshold. Defines the SYSLEV voltage
threshold. See the Programmable System Voltage Monitor
section for more information.
SYS
SYS
SYS
SYS
SYS
0x00
0x01
0x01
0x01
0x01
[3:0]
[7:6]
[5]
SYSLEV
R/W
R/W
R/W
R/W
R/W
-
Reserved.
DEEP-SLEEP Enable Bit. Set bit to 1 to enter DEEP-SLEEP
mode, clear bit to 0 to wake from DEEP-SLEEP. Bit
automatically cleared to 0 when PBIN asserted.
PWRDS
-
[4]
Reserved.
Scratchpad Bits. Non-functional bits, maybe be used by user to
store system status information. Volatile bits, which are cleared
when system voltage falls below UVLO threshold.
[3:2]
SCRATCH
Deep-Sleep Ready Flag. Set bit to 1 before entering DEEP-
SLEEP mode, then read bit during enable sequence to identify
system status: if bit value is 1 the system is waking from DEEP-
SLEEP mode, if bit value is 0 the system is waking from a
disabled state.
SYS
0x01
[1]
DSRDY
R/W
R/W
Shutdown Request Flag. Set the bit value right after start-up
then microprocessor could check whenever the second push-
button is asserted.
SYS
0x01
[0]
SDREQ
REG1
REG1
REG1
REG1
0x20
0x20
0x21
0x22
[7:6]
[5:0]
[7:0]
[7]
-
VSET
-
R
Reserved.
Output Voltage Selection. See the Output Voltage Programming
section for more information.
R/W
R
Reserved.
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear
bit to 0 to disable the regulator.
ON
R/W
Regulator Phase Control. Set bit to 1 for the regulator to operate
180° out of phase with the oscillator, clear bit to 0 for the
regulator to operate in phase with the oscillator.
REG1
REG1
0x22
0x22
[6]
[5]
PHASE
MODE
R/W
R/W
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM
under all load conditions, clear bit to 0 to transit to power-
savings mode under light-load conditions.
Regulator Turn-On Delay Control. See the REG1, REG2, REG3
Turn-on Delay section for more information.
REG1
REG1
REG1
0x22
0x22
0x22
[4:2]
[1]
DELAY
nFLTMSK
OK
R/W
R/W
R
Regulator Fault Mask Control. Set bit to 1 enable fault-interrupts,
clear bit to 0 to disable fault-interrupts.
Regulator Power-OK Status. Value is 1 when output voltage
exceeds the power-OK threshold, value is 0 otherwise.
[0]
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