ACT8935
Rev 4, 17-Sep-13
unmasked via the I2C interface. For more
information about the available fault conditions,
refer to the appropriate sections of this datasheet.
PWRHLD, holding REG1, REG2, and REG5, and
assert PWREN (X_PWR_EN), enabling REG4,
REG6, REG7 and holding REG3 to ensure that the
system remains powered after PBIN is released.
Note that under some conditions a false interrupt
may be generated upon initial startup. For this
reason, it is recommended that the interrupt service
routine check and validate nSYSLEVMSK[-] and
nFLTMSK[-] bits before processing an interrupt
generated by these bits. These interrupts may be
validated by nSYSSTAT[-], OK[-] bits.
The logic required to control the Prima and Atlas IV
processors requires that REG3 is enabled when
PBIN is asserted during power-up, but then operate
independently of PBIN during SLEEP mode. For
this reason, the ACT8935 features the
REG3/PWRSTAT[-] bit, which controls how REG3
responds when the PBIN input is asserted. The
required functionality may be achieved either by
setting PWRSTAT[-] to 1 during the boot sequence
or, alternatively, as part of the process of entering
SLEEP mode.
Push-Button Control
The ACT8935 is designed to initiate a system
enable sequence when the PBIN multi-function
input is asserted. Once this occurs, a power-on
sequence commences, as described below. The
power-on sequence must complete and the
microprocessor must take control (by asserting
PWREN or PWRHLD) before PBIN is de-asserted.
If the microprocessor is unable to complete its
power-up routine successfully before the user
releases the push-button, the ACT8935
automatically shuts the system down. This provides
protection against accidental or momentary
assertions of the push-button. If desired, longer
“push-and-hold” times can be implemented by
simply adding an additional time delay before
asserting PWREN or PWRHLD.
Once the power-up routine is completed, the
system remains enabled after the push-button is
released as long as either PWRHLD or PWREN are
asserted high. If the processor does not assert
PWRHLD or PWREN before the user releases the
push-button, the boot-up sequence is terminated
and all regulators are disabled. This provides
protection against "false-enable", when the push-
button is accidentally depressed, and also ensures
that the system remains enabled only if the
processor successfully completes the boot-up
sequence.
Alternatively, an enable sequence may initiate as a
result of asserting the EXTON input. EXTON
enables the ACT8935 in an identical manner as
PBIN, but does not assert nPBSTAT. EXTON is
normally driven by the Prima/Atlas IV's RTC Alarm
signal in order to enable or wake the system from
SLEEP, DEEP-SLEEP, or shut down modes.
Control Sequences
The ACT8935 features
a
variety of control
sequences that are optimized for supporting system
enable and disable, as well as both SLEEP and
DEEP-SLEEP modes of the SiRF Prima and Atlas
IV processors.
Enable Sequence
A typical enable sequence initiates as a result of
asserting PBIN, and begins by enabling REG3 and
REG5. When REG5 reaches its power-OK
threshold, REG1 and REG2 are enabled and
nRSTO is asserted low, resetting the
microprocessor. If REG5 is above its power-OK
threshold when the reset timer expires, nRSTO is
de-asserted, allowing the microprocessor to begin
its boot sequence.
During the boot sequence, the processor should
read the DSRDY[ ] bit; if the value of DSRDY[ ] is 0
then the software should proceed with a typical
enable sequence, whereas if the value of DSRDY[-]
is 1 then the software should proceed with a “wake
from DEEP-SLEEP” routine. See the DEEP-SLEEP
Sequence section for more information. During the
boot sequence, the microprocessor must assert
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