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ACT8933QJ233-T 参数 Datasheet PDF下载

ACT8933QJ233-T图片预览
型号: ACT8933QJ233-T
PDF下载: 下载PDF文件 查看货源
内容描述: [Advanced PMU for CoreLogic LUCY]
分类和应用:
文件页数/大小: 44 页 / 723 K
品牌: ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
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ACT8933  
Rev 3, 15-Nov-12  
LOW-NOISE, LOW-DROPOUT LINEAR REGULATORS  
falling edge of ON[ ] bit as on/off signal. To enable  
the regulator, clear ON[ ] to 0 first then set to 1. To  
disable the regulator, set ON[ ] to 1 first then clear it  
to 0.  
General Description  
REG4, REG5, REG6, and REG7 are low-noise,  
low-dropout linear regulators (LDOs) that are each  
capable of supplying up to 250mA. Each LDO has  
been optimized to achieve low noise and high-  
PSRR, achieving more than 65dB PSRR at  
frequencies up to 10kHz.  
REG4, REG5, REG6, REG7 Turn-on Delay  
Each of REG4, REG5, REG6 and REG7 features a  
programmable Turn-on Delay which help ensure a  
reliable qualification. This delay is programmed by  
DELAY[2:0], as shown in Table 7.  
Output Current Limit  
Each LDO contains current-limit circuitry featuring a  
current-limit fold-back function. During normal and  
moderate overload conditions, the regulators can  
support more than their rated output currents.  
During extreme overload conditions, however, the  
current limit is reduced by approximately 30%,  
reducing power dissipation within the IC.  
Output Discharge  
Each of the ACT8933’s LDOs features an optional  
output discharge function, which discharges the  
output to ground through a 1.5kresistance when  
the LDO is disabled. This feature may be enabled  
or disabled by setting DIS[-]; set DIS[-] to 1 to  
enable this function, clear DIS[-] to 0 to disable it.  
Compensation  
Low-Power Mode  
The LDOs are internally compensated and require  
very little design effort, simply select input and  
output capacitors according to the guidelines below.  
Each of ACT8933's LDOs features a LOWIQ[-] bit  
which, when set to 1, reduces the LDO's quiescent  
current by about 16%, saving power and extending  
battery lifetime.  
Input Capacitor Selection  
Each LDO requires a small ceramic input capacitor  
to supply current to support fast transients at the  
input of the LDO. Bypassing each INL pin to GA  
with 1μF. High quality ceramic capacitors such as  
X7R and X5R dielectric types are strongly  
recommended.  
OK[ ] and Output Fault Interrupt  
Each LDO features a power-OK status bit that can  
be read by the system microprocessor via the  
interface. If an output voltage is lower than the  
power-OK threshold, typically 11% below the  
programmed regulation voltage, the value of that  
regulator's OK[-] bit will be 0.  
Output Capacitor Selection  
Each LDO requires a small 2.2μF ceramic output  
capacitor for stability. For best performance, each  
output capacitor should be connected directly  
between the output and GA pins, as close to the  
output as possible, and with a short, direct  
connection. High quality ceramic capacitors such as  
X7R and X5R dielectric types are strongly  
recommended.  
If a LDO's nFLTMSK[-] bit is set to 1, the ACT8933  
will interrupt the processor if that LDO's output  
voltage falls below the power-OK threshold. In this  
case, nIRQ will assert low and remain asserted until  
either the regulator is turned off or back in  
regulation, and the OK[-] bit has been read via I2C.  
PCB Layout Considerations  
Configuration Options  
The ACT8933’s LDOs provide good DC, AC, and  
noise performance over a wide range of operating  
conditions, and are relatively insensitive to layout  
considerations. When designing a PCB, however,  
careful layout is necessary to prevent other circuitry  
from degrading LDO performance.  
Output Voltage Programming  
By default, each LDO powers up and regulates to  
its default output voltage. Once the system is  
enabled, each output voltage may be independently  
programmed to a different value by writing to the  
regulator's VSET[-] register via the I2C serial  
interface as shown in Table 8.  
A good design places input and output capacitors  
as close to the LDO inputs and output as possible,  
and utilizes a star-ground configuration for all  
regulators to prevent noise-coupling through  
ground. Output traces should be routed to avoid  
close proximity to noisy nodes, particularly the SW  
nodes of the DC/DCs.  
Enable / Disable Control  
During normal operation, each LDO may be  
enabled or disabled via the I2C interface by writing  
to that LDO's ON[ ] bit. The regulator accept rising or  
Innovative PowerTM  
www.active-semi.com  
- 35 -  
Active-Semi ProprietaryFor Authorized Recipients and Customers  
ActivePMUTM and ActivePathTM are trademarks of Active-Semi.  
I2CTM is a trademark of NXP.  
Copyright © 2012 Active-Semi, Inc.  
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