ACT8933
Rev 3, 15-Nov-12
upon startup or when manual reset is asserted via
the nPBIN input. When asserted on startup, nRSTO
remains low until reset time-out period expires after
OUT5 reaches its power-OK threshold. When
asserted due to manual-reset, nRSTO immediately
asserts low, then remains asserted low until the
nPBIN input is de-asserted and the reset time-out
period expires.
Enabling/Disabling Sequence
A typical enable sequence is initiated whenever the
following conditions occurs:
1) nPBIN is asserted low via 50Kꢀ resistance, or
2) A valid input voltage is present at CHGINꢀ.
The enable sequence begins by enabling REG1.
When REG1 reaches its power-OK threshold,
REG2 and REG5 are enabled and nRSTO is
asserted low, resetting the microprocessor. If REG1
is above its power-OK threshold when the reset
timer expires, nRSTO is de-asserted, allowing the
microprocessor to begin its boot sequence.
Connect a 10kꢀ or greater pull-up resistor from
nRSTO to an appropriate voltage supply (typically
OUT5).
nIRQ Output
nIRQ is an open-drain output that asserts low any
time an interrupt is generated. Connect a 10kꢀ or
greater pull-up resistor from nIRQ to an appropriate
voltage supply. nIRQ is typically used to drive the
interrupt input of the system processor.
During the boot sequence, the microprocessor must
assert PWRHLD, holding REG1, REG2, and REG5,
and assert PWREN (PWR_EN), enabling REG3
and REG4 to ensure that the system remains
powered after nPBIN is released. REG6 and REG7
should be enabled/disabled via I2C after
microprocessor completes its boot sequence.
Many of the ACT8933's functions support interrupt-
generation as a result of various conditions. These
are typically masked by default, but may be
unmasked via the I2C interface. For more
information about the available fault conditions,
refer to the appropriate sections of this datasheet.
Once the power-up routine is completed, the
system remains enabled after the push-button is
released as long as either PWRHLD or PWREN are
asserted high. If the processor does not assert
PWRHLD or PWREN before the user releases the
push-button, the boot-up sequence is terminated
and all regulators are disabled. This provides
protection against "false-enable", when the push-
button is accidentally depressed, and also ensures
that the system remains enabled only if the
processor successfully completes the boot-up
sequence.
Note that under some conditions a false interrupt
may be generated upon initial startup. For this
reason, it is recommended that the interrupt service
routine check and validate nSYSLEVMSK[-] and
nFLTMSK[-] bits before processing an interrupt
generated by these bits. These interrupts may be
validated by nSYSSTAT[-], OK[-] bits.
Push-Button Control
As with the enable sequence, a typical disable
sequence is initiated when the user presses the
push-button, which interrupts the processor via the
nPBSTAT output. The actual disable sequence is
completely software-controlled, but typically
involved initiating various “clean-up” processes then
finally de-assert PWRHLD and PWREN, disabling
all regulators and shutting the system down.
The ACT8933 is designed to initiate a system
enable sequence when the nPBIN multi-function
input is asserted. Once this occurs, a power-on
sequence commences, as described below. The
power-on sequence must complete and the
microprocessor must take control (by asserting
PWREN or PWRHLD) before nPBIN is de-asserted.
If the microprocessor is unable to complete its
power-up routine successfully before the user
releases the push-button, the ACT8933
automatically shuts the system down. This provides
protection against accidental or momentary
assertions of the push-button. If desired, longer
“push-and-hold” times can be implemented by
simply adding an additional time delay before
asserting PWREN or PWRHLD.
SLEEP Mode Sequence
The ACT8933 supports CoreLogic LUCY
Processor’s SLEEP mode operation. Once a
successful power-up routine has been completed,
SLEEP mode may be initiated through a variety of
software-controlled mechanisms.
SLEEP mode is typically initiated when the user
presses the push-button during normal operation.
Pressing the push-button asserts the nPBIN input,
which asserts the nPBSTAT output, which
interrupts the processor. In response to this
interrupt the processor should de-assert PWREN,
disabling REG3 and REG4. PWRHLD should
remain asserted during SLEEP mode so that
Control Sequences
The ACT8933 features
sequences that are optimized for supporting system
enable and disable, as well as SLEEP mode of the
CoreLogic LUCY processor.
a
variety of control
ꢀ: Applicable only for ACT8933QJ2XX .
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