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ACT8897Q4I106-T 参数 Datasheet PDF下载

ACT8897Q4I106-T图片预览
型号: ACT8897Q4I106-T
PDF下载: 下载PDF文件 查看货源
内容描述: [Advanced PMU for Samsung S5PC100, S5PC110 and S5PV210 Processors]
分类和应用: PC
文件页数/大小: 32 页 / 595 K
品牌: ACTIVE-SEMI [ ACTIVE-SEMI, INC ]
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ACT8897  
Rev 2, 05-Sep-13  
REGISTER AND BIT DESCRIPTIONS  
Table 1:  
Global Register Map  
OUTPUT ADDRESS BIT  
NAME  
ACCESS  
DESCRIPTION  
Reset Timer Setting. Defines the reset time-out threshold. Reset  
time-out is 65ms when value is 1, reset time-out is 260ms when  
value is 0. See nRSTO Output section for more information.  
SYS  
SYS  
0x00  
0x00  
[7]  
TRST  
R/W  
SYSLEV Mode Select. Defines the response to the SYSLEV  
voltage detector, 1: Generate an interrupt when VVDDREF falls  
below the programmed SYSLEV threshold, 0: automatic  
shutdown when VVDDREF falls below the programmed SYSLEV  
threshold.  
[6] nSYSMODE  
R/W  
System Voltage Level Interrupt Mask. Disabled interrupt by  
default, set to 1 to enable this interrupt. See the Programmable  
System Voltage Monitor section for more information  
SYS  
SYS  
0x00  
0x00  
[5] nSYSLEVMSK R/W  
System Voltage Status. Value is 1 when VVDDREF is lower than the  
SYSLEV voltage threshold, value is 0 when VVDDREF is higher  
than the system voltage detection threshold.  
[4]  
nSYSSTAT  
R
System Voltage Detect Threshold. Defines the SYSLEV voltage  
threshold. See the Programmable System Voltage Monitor  
section for more information.  
SYS  
SYS  
0x00  
0x01  
0x01  
0x20  
0x20  
0x21  
0x21  
[3:0]  
[7:4]  
SYSLEV  
-
R/W  
R/W  
R/W  
R
Reserved.  
Scratchpad Bits. Non-functional bits, maybe be used by user to  
store system status information. Volatile bits, which are cleared  
upon system shutdown.  
SYS  
[3:0] SCRATCH  
REG1  
REG1  
REG1  
REG1  
[7:6]  
[5:0]  
[7:6]  
[5:0]  
-
Reserved.  
Primary Output Voltage Selection. Valid when VSEL is driven low.  
See the Output Voltage Programming section for more  
information.  
VSET1  
-
R/W  
R
Reserved.  
Secondary Output Voltage Selection. Valid when VSEL is driven  
high. See the Output Voltage Programming section for more  
information.  
VSET2  
R/W  
Regulator Enable Bit. Set bit to 1 to enable the regulator, clear bit  
to 0 to disable the regulator.  
REG1  
REG1  
0x22  
0x22  
[7]  
[6]  
ON  
R/W  
R/W  
Regulator Phase Control. Set bit to 1 for regulator to operate  
180° out of phase with the oscillator, clear bit to 0 for regulator to  
operate in phase with the oscillator.  
PHASE  
Regulator Mode Select. Set bit to 1 for fixed-frequency PWM  
under all load conditions, clear bit to 0 to transit to power-savings  
mode under light-load conditions.  
REG1  
0x22  
[5]  
MODE  
R/W  
Regulator Turn-On Delay Control. See the REG1, REG2, REG3  
Turn-on Delay section for more information.  
REG1  
REG1  
0x22  
0x22  
[4:2]  
[1]  
DELAY  
R/W  
R/W  
Regulator Fault Mask Control. Set bit to 1 enable to fault-  
interrupts, clear bit to 0 to disable fault-interrupts.  
nFLTMSK  
Regulator Power-OK Status. Value is 1 when output voltage  
exceeds the power-OK threshold, value is 0 otherwise.  
REG1  
REG2  
0x22  
0x30  
[0]  
OK  
-
R
[7:6]  
Reserved.  
R
Primary Output Voltage Selection. Valid when VSEL is driven low.  
See the Output Voltage Programming section for more  
information.  
REG2  
REG2  
REG2  
0x30  
0x31  
0x31  
[5:0]  
[7:6]  
[5:0]  
VSET1  
-
R/W  
R
Reserved.  
Secondary Output Voltage Selection. Valid when VSEL is driven  
high. See the Output Voltage Programming section for more  
information.  
VSET2  
R/W  
Innovative PowerTM  
www.active-semi.com  
- 10 -  
Active-Semi ProprietaryFor Authorized Recipients and Customers  
ActivePMUTM is trademark of Active-Semi.  
Copyright © 2013 Active-Semi, Inc.  
I2CTM is a trademark of NXP.