ACT8892
Rev 2, 01-Jul-15
response to this interrupt the processor should first
set the FRC_ON1[ ] bit to 1, and the HBRDY[ ] bit to
1. Then the processor should de-assert PWREN
and PWRHLD, disabling REG2, REG3, REG4,
REG5, REG6 and REG7.
wake process, the processor should assert
PWRHLD, holding REG1, REG2 and REG3 to
ensure that the system remains enabled after the
push-button is released then set FRC_ON1[ ] and
HBRDY[ ] to 0 to complete a full wake-up routine.
Waking from Hibernate mode is initiated when the
user presses the push-button again. Asserting
nPBIN enables REG1, REG2, and REG3. When
REG3 reaches its power-OK threshold, nRSTO is
asserted low, resetting the microprocessor. REG2
is enabled after REG3 reaches its power-OK
threshold for 4ms. Once the reset timer period
expires the nRSTO output is de-asserted and the
processor initiates a boot-up sequence, during
which it should determine the system status by
reading the HBRDY[ ] bit; if the value of HBRDY[ ]
is 0 then the software should proceed with a typical
enable sequence, whereas if the value of HBRDY[ ]
is 1 then the software should proceed with a “wake
from Hibernate Mode” routine. To complete the
Disable Sequence
As with the enable sequence, a typical disable
sequence is initiated when the user presses the
push-button, which interrupts the processor via the
nPBSTAT output. The actual disable sequence is
completely
software-controlled,
but
typically
involved initiating various “clean-up” processes
before finally de-assert PWREN and PWRHLD,
disabling all regulators and shutting the system
down. It is important that FRC_ON1[ ] is clear to 0
prior to shutting down the system, otherwise REG1
will remain ON.
Figure 3:
Enable/Disable Sequence for ACT8892Q4I134-T
Shutdown
Sequence
Power Up Sequence
nPBIN
nPBSTAT
93% of regulation
OUT3
2ms
OUT1
OUT2
4ms
260ms
nRSTO
PWRHLD
PWREN
OUT4, OUT5, OUT6, OUT7
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